derek.holloway
7502bf64a4
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66 lines
2.0 KiB
LLVM
66 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32ZBS
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; RUN: llc -mtriple=riscv32 -mattr=+zbs,+xqcibm -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32ZBSXQCIBM
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define signext i32 @bexti_hints(i32 %a, i32 signext %b, i32 %c) nounwind {
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; RV32I-LABEL: bexti_hints:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 26
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; RV32I-NEXT: srli a1, a1, 31
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; RV32I-NEXT: addi a0, a1, 2047
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; RV32I-NEXT: addi a0, a0, 1286
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; RV32I-NEXT: ret
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;
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; RV32ZBS-LABEL: bexti_hints:
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; RV32ZBS: # %bb.0:
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; RV32ZBS-NEXT: bexti a0, a1, 5
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; RV32ZBS-NEXT: addi a0, a0, 2047
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; RV32ZBS-NEXT: addi a0, a0, 1286
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; RV32ZBS-NEXT: ret
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;
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; RV32ZBSXQCIBM-LABEL: bexti_hints:
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; RV32ZBSXQCIBM: # %bb.0:
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; RV32ZBSXQCIBM-NEXT: bexti a1, a1, 5
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; RV32ZBSXQCIBM-NEXT: addi a0, a1, 2047
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; RV32ZBSXQCIBM-NEXT: addi a0, a0, 1286
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; RV32ZBSXQCIBM-NEXT: ret
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%and = and i32 %b, 32
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%cmp = icmp ne i32 %and, 0
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%zext = zext i1 %cmp to i32
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%add = add i32 %zext, 3333
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ret i32 %add
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}
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define i32 @bseti_hints(i32 %a, i32 %b, i32 %c) nounwind {
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; RV32I-LABEL: bseti_hints:
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; RV32I: # %bb.0:
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; RV32I-NEXT: li a0, 1
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; RV32I-NEXT: slli a0, a0, 11
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; RV32I-NEXT: or a1, a1, a0
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: addi a0, a0, 1285
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; RV32I-NEXT: ret
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;
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; RV32ZBS-LABEL: bseti_hints:
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; RV32ZBS: # %bb.0:
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; RV32ZBS-NEXT: bseti a0, a1, 11
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; RV32ZBS-NEXT: addi a0, a0, 2047
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; RV32ZBS-NEXT: addi a0, a0, 1286
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; RV32ZBS-NEXT: ret
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;
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; RV32ZBSXQCIBM-LABEL: bseti_hints:
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; RV32ZBSXQCIBM: # %bb.0:
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; RV32ZBSXQCIBM-NEXT: bseti a1, a1, 11
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; RV32ZBSXQCIBM-NEXT: addi a0, a1, 2047
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; RV32ZBSXQCIBM-NEXT: addi a0, a0, 1286
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; RV32ZBSXQCIBM-NEXT: ret
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%or = or i32 %b, 2048
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%add = add i32 %or, 3333
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ret i32 %add
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}
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