TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/xtheadfmemidx.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d,+xtheadfmemidx \
; RUN:   -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,RV32XTHEADFMEMIDX
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d,+xtheadfmemidx \
; RUN:   -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,RV64XTHEADFMEMIDX

define float @flrw(ptr %a, iXLen %b) {
; CHECK-LABEL: flrw:
; CHECK:       # %bb.0:
; CHECK-NEXT:    th.flrw fa5, a0, a1, 2
; CHECK-NEXT:    fadd.s fa0, fa5, fa5
; CHECK-NEXT:    ret
  %1 = getelementptr float, ptr %a, iXLen %b
  %2 = load float, ptr %1, align 4
  %3 = fadd float %2, %2
  ret float %3
}

define float @flurw(ptr %a, i32 %b) {
; RV32XTHEADFMEMIDX-LABEL: flurw:
; RV32XTHEADFMEMIDX:       # %bb.0:
; RV32XTHEADFMEMIDX-NEXT:    th.flrw fa5, a0, a1, 2
; RV32XTHEADFMEMIDX-NEXT:    fadd.s fa0, fa5, fa5
; RV32XTHEADFMEMIDX-NEXT:    ret
;
; RV64XTHEADFMEMIDX-LABEL: flurw:
; RV64XTHEADFMEMIDX:       # %bb.0:
; RV64XTHEADFMEMIDX-NEXT:    th.flurw fa5, a0, a1, 2
; RV64XTHEADFMEMIDX-NEXT:    fadd.s fa0, fa5, fa5
; RV64XTHEADFMEMIDX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr float, ptr %a, i64 %1
  %3 = load float, ptr %2, align 4
  %4 = fadd float %3, %3
  ret float %4
}

define void @fsrw(ptr %a, iXLen %b, float %c) {
; CHECK-LABEL: fsrw:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fadd.s fa5, fa0, fa0
; CHECK-NEXT:    th.fsrw fa5, a0, a1, 2
; CHECK-NEXT:    ret
  %1 = fadd float %c, %c
  %2 = getelementptr float, ptr %a, iXLen %b
  store float %1, ptr %2, align 4
  ret void
}

define void @fsurw(ptr %a, i32 %b, float %c) {
; RV32XTHEADFMEMIDX-LABEL: fsurw:
; RV32XTHEADFMEMIDX:       # %bb.0:
; RV32XTHEADFMEMIDX-NEXT:    fadd.s fa5, fa0, fa0
; RV32XTHEADFMEMIDX-NEXT:    th.fsrw fa5, a0, a1, 2
; RV32XTHEADFMEMIDX-NEXT:    ret
;
; RV64XTHEADFMEMIDX-LABEL: fsurw:
; RV64XTHEADFMEMIDX:       # %bb.0:
; RV64XTHEADFMEMIDX-NEXT:    fadd.s fa5, fa0, fa0
; RV64XTHEADFMEMIDX-NEXT:    th.fsurw fa5, a0, a1, 2
; RV64XTHEADFMEMIDX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = fadd float %c, %c
  %3 = getelementptr float, ptr %a, i64 %1
  store float %2, ptr %3, align 4
  ret void
}

define double @flrd(ptr %a, iXLen %b) {
; CHECK-LABEL: flrd:
; CHECK:       # %bb.0:
; CHECK-NEXT:    th.flrd fa5, a0, a1, 3
; CHECK-NEXT:    fadd.d fa0, fa5, fa5
; CHECK-NEXT:    ret
  %1 = getelementptr double, ptr %a, iXLen %b
  %2 = load double, ptr %1, align 8
  %3 = fadd double %2, %2
  ret double %3
}

define double @flurd(ptr %a, i32 %b) {
; RV32XTHEADFMEMIDX-LABEL: flurd:
; RV32XTHEADFMEMIDX:       # %bb.0:
; RV32XTHEADFMEMIDX-NEXT:    th.flrd fa5, a0, a1, 3
; RV32XTHEADFMEMIDX-NEXT:    fadd.d fa0, fa5, fa5
; RV32XTHEADFMEMIDX-NEXT:    ret
;
; RV64XTHEADFMEMIDX-LABEL: flurd:
; RV64XTHEADFMEMIDX:       # %bb.0:
; RV64XTHEADFMEMIDX-NEXT:    th.flurd fa5, a0, a1, 3
; RV64XTHEADFMEMIDX-NEXT:    fadd.d fa0, fa5, fa5
; RV64XTHEADFMEMIDX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = getelementptr double, ptr %a, i64 %1
  %3 = load double, ptr %2, align 8
  %4 = fadd double %3, %3
  ret double %4
}

define void @fsrd(ptr %a, iXLen %b, double %c) {
; CHECK-LABEL: fsrd:
; CHECK:       # %bb.0:
; CHECK-NEXT:    fadd.d fa5, fa0, fa0
; CHECK-NEXT:    th.fsrd fa5, a0, a1, 3
; CHECK-NEXT:    ret
  %1 = fadd double %c, %c
  %2 = getelementptr double, ptr %a, iXLen %b
  store double %1, ptr %2, align 8
  ret void
}

define void @fsurd(ptr %a, i32 %b, double %c) {
; RV32XTHEADFMEMIDX-LABEL: fsurd:
; RV32XTHEADFMEMIDX:       # %bb.0:
; RV32XTHEADFMEMIDX-NEXT:    fadd.d fa5, fa0, fa0
; RV32XTHEADFMEMIDX-NEXT:    th.fsrd fa5, a0, a1, 3
; RV32XTHEADFMEMIDX-NEXT:    ret
;
; RV64XTHEADFMEMIDX-LABEL: fsurd:
; RV64XTHEADFMEMIDX:       # %bb.0:
; RV64XTHEADFMEMIDX-NEXT:    fadd.d fa5, fa0, fa0
; RV64XTHEADFMEMIDX-NEXT:    th.fsurd fa5, a0, a1, 3
; RV64XTHEADFMEMIDX-NEXT:    ret
  %1 = zext i32 %b to i64
  %2 = fadd double %c, %c
  %3 = getelementptr double, ptr %a, i64 %1
  store double %2, ptr %3, align 8
  ret void
}