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217 lines
6.5 KiB
YAML
217 lines
6.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# NOTE: Test expansion of PseudoLD_RV32_OPT/PseudoSD_RV32_OPT after register allocation
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# RUN: llc -mtriple=riscv32 -mattr=+zilsd -run-pass riscv-load-store-opt %s -o - | FileCheck %s
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--- |
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define i32 @expand_pseudold_valid(ptr %0) {
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%2 = load i32, ptr %0, align 4
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%3 = getelementptr inbounds i32, ptr %0, i32 1
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%4 = load i32, ptr %3, align 4
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%5 = add i32 %2, %4
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ret i32 %5
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}
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define void @expand_pseudosd_valid(ptr %0, i32 %1, i32 %2) {
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store i32 %1, ptr %0, align 4
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%4 = getelementptr inbounds i32, ptr %0, i32 1
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store i32 %2, ptr %4, align 4
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ret void
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}
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define i32 @expand_pseudold_invalid_pair(ptr %0) {
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%2 = load i32, ptr %0, align 4
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%3 = getelementptr inbounds i32, ptr %0, i32 1
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%4 = load i32, ptr %3, align 4
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%5 = add i32 %2, %4
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ret i32 %5
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}
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define void @expand_pseudosd_invalid_pair(ptr %0, i32 %1, i32 %2) {
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store i32 %1, ptr %0, align 4
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%4 = getelementptr inbounds i32, ptr %0, i32 1
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store i32 %2, ptr %4, align 4
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ret void
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}
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define void @store_zero_combine_valid(ptr %0) {
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store i32 0, ptr %0, align 8
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%2 = getelementptr inbounds i32, ptr %0, i32 1
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store i32 0, ptr %2, align 8
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ret void
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}
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define void @store_zero_combine_invalid(ptr %0, i32 %1) {
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store i32 %1, ptr %0, align 8
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%3 = getelementptr inbounds i32, ptr %0, i32 1
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store i32 0, ptr %3, align 8
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ret void
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}
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@global_array = external global [100 x i32]
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define i32 @expand_pseudold_invalid_symbolic() {
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ret i32 0
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}
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define i32 @overlapped_first_reg_base_reg() {
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ret i32 0
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}
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...
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---
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# Valid consecutive even/odd register pair - should expand to LD_RV32
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name: expand_pseudold_valid
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tracksRegLiveness: false
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body: |
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bb.0:
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liveins: $x10
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; PseudoLD_RV32_OPT with consecutive even/odd registers (x12, x13)
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; CHECK-LABEL: name: expand_pseudold_valid
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x12_x13 = LD_RV32 killed $x10, 0
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; CHECK-NEXT: $x10 = ADD killed $x12, killed $x13
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; CHECK-NEXT: PseudoRET implicit $x10
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$x12, $x13 = PseudoLD_RV32_OPT killed $x10, 0
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$x10 = ADD killed $x12, killed $x13
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PseudoRET implicit $x10
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...
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---
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# Valid consecutive even/odd register pair - should expand to SD_RV32
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name: expand_pseudosd_valid
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tracksRegLiveness: false
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body: |
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bb.0:
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liveins: $x10, $x12, $x13
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; PseudoSD_RV32_OPT with consecutive even/odd registers (x12, x13)
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; CHECK-LABEL: name: expand_pseudosd_valid
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; CHECK: liveins: $x10, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: SD_RV32 killed $x12_x13, killed $x10, 0
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; CHECK-NEXT: PseudoRET
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PseudoSD_RV32_OPT killed $x12, killed $x13, killed $x10, 0
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PseudoRET
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...
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---
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# Invalid register pair (not consecutive) - should decompose back to LW
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name: expand_pseudold_invalid_pair
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tracksRegLiveness: false
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body: |
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bb.0:
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liveins: $x10
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; PseudoLD_RV32_OPT with non-consecutive registers (x11, x13)
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; Should decompose back to two LW instructions
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; CHECK-LABEL: name: expand_pseudold_invalid_pair
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x11 = LW $x10, 0
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; CHECK-NEXT: $x13 = LW killed $x10, 4
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; CHECK-NEXT: $x10 = ADD killed $x11, killed $x13
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; CHECK-NEXT: PseudoRET implicit $x10
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$x11, $x13 = PseudoLD_RV32_OPT killed $x10, 0
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$x10 = ADD killed $x11, killed $x13
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PseudoRET implicit $x10
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...
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---
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# Invalid register pair (not even/odd) - should decompose back to SW
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name: expand_pseudosd_invalid_pair
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tracksRegLiveness: false
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body: |
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bb.0:
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liveins: $x10, $x11, $x14
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; PseudoSD_RV32_OPT with non-consecutive registers (x11, x14)
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; Should decompose back to two SW instructions
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; CHECK-LABEL: name: expand_pseudosd_invalid_pair
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; CHECK: liveins: $x10, $x11, $x14
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: SW killed $x11, $x10, 0
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; CHECK-NEXT: SW killed $x14, killed $x10, 4
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; CHECK-NEXT: PseudoRET
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PseudoSD_RV32_OPT killed $x11, killed $x14, killed $x10, 0
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PseudoRET
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...
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---
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# Test store zero combinations - zeros don't need consecutive pairs
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name: store_zero_combine_valid
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tracksRegLiveness: false
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: store_zero_combine_valid
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: SD_RV32 $x0_pair, killed $x10, 0
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; CHECK-NEXT: PseudoRET
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PseudoSD_RV32_OPT $x0, $x0, killed $x10, 0
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PseudoRET
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...
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---
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# Test store zero base combinations - zero can't be first register unless both
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# are zeros
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name: store_zero_combine_invalid
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tracksRegLiveness: false
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: store_zero_combine_invalid
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: SW killed $x0, $x10, 0
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; CHECK-NEXT: SW killed $x1, killed $x10, 4
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; CHECK-NEXT: PseudoRET
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PseudoSD_RV32_OPT killed $x0, killed $x1, killed $x10, 0
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PseudoRET
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...
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---
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# Test invalid register pair with symbolic operands - should split back to LW
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name: expand_pseudold_invalid_symbolic
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tracksRegLiveness: false
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body: |
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bb.0:
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liveins: $x10
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; PseudoLD_RV32_OPT with symbolic operand and non-consecutive registers (x11, x14)
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; Should decompose back to two LW instructions preserving symbolic references
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; CHECK-LABEL: name: expand_pseudold_invalid_symbolic
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x11 = LW $x10, target-flags(riscv-lo) @global_array
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; CHECK-NEXT: $x14 = LW killed $x10, target-flags(riscv-lo) @global_array + 4
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; CHECK-NEXT: $x10 = ADD killed $x11, killed $x14
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; CHECK-NEXT: PseudoRET implicit $x10
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$x11, $x14 = PseudoLD_RV32_OPT killed $x10, target-flags(riscv-lo) @global_array
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$x10 = ADD killed $x11, killed $x14
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PseudoRET implicit $x10
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...
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---
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# Test overlapped first reg and base reg - should split back to LW
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name: overlapped_first_reg_base_reg
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tracksRegLiveness: false
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body: |
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bb.0:
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liveins: $x10
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; PseudoLD_RV32_OPT with first destination register overlapping base register ($x11)
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; Should decompose back to two LW instructions when first reg overlaps base reg
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; CHECK-LABEL: name: overlapped_first_reg_base_reg
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x14 = LW $x11, 4
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; CHECK-NEXT: $x11 = LW killed $x11, 0
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; CHECK-NEXT: $x10 = ADD killed $x11, killed $x14
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; CHECK-NEXT: PseudoRET implicit $x10
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$x11, $x14 = PseudoLD_RV32_OPT killed $x11, 0
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$x10 = ADD killed $x11, killed $x14
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PseudoRET implicit $x10
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...
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