derek.holloway
7502bf64a4
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89 lines
3.6 KiB
LLVM
89 lines
3.6 KiB
LLVM
; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - --asm-verbose=0 | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
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target triple = "spirv-unknown-vulkan1.3-compute"
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define internal spir_func void @main() #3 {
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; CHECK-DAG: OpName %[[#switch_0:]] "reg1"
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; CHECK-DAG: OpName %[[#switch_1:]] "reg"
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; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0
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; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1
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; CHECK: %[[#entry:]] = OpLabel
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; CHECK-DAG: %[[#switch_0]] = OpVariable %[[#]] Function
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; CHECK-DAG: %[[#switch_1]] = OpVariable %[[#]] Function
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; CHECK: OpSelectionMerge %[[#merge:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#new_header:]] %[[#unreachable:]]
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; CHECK: %[[#unreachable]] = OpLabel
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; CHECK-NEXT: OpUnreachable
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; CHECK: %[[#new_header]] = OpLabel
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; CHECK: OpSelectionMerge %[[#new_merge:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#taint_true_merge:]] %[[#br_false:]]
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; CHECK: %[[#br_false]] = OpLabel
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; CHECK-DAG: OpStore %[[#switch_1]] %[[#int_0]]
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; CHECK: OpSelectionMerge %[[#taint_merge:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#taint_merge]] %[[#taint_false:]]
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; CHECK: %[[#taint_false]] = OpLabel
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; CHECK: OpStore %[[#switch_1]] %[[#int_1]]
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; CHECK: OpBranch %[[#taint_merge]]
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; CHECK: %[[#taint_merge]] = OpLabel
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; CHECK: OpStore %[[#switch_0]] %[[#int_0]]
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; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#switch_1]]
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; CHECK: %[[#cond:]] = OpIEqual %[[#]] %[[#int_0]] %[[#tmp]]
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; CHECK: OpBranchConditional %[[#cond]] %[[#taint_false_true:]] %[[#new_merge]]
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; CHECK: %[[#taint_false_true]] = OpLabel
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; CHECK: OpStore %[[#switch_0]] %[[#int_1]]
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; CHECK: OpBranch %[[#new_merge]]
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; CHECK: %[[#taint_true_merge]] = OpLabel
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; CHECK: OpStore %[[#switch_0]] %[[#int_1]]
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; CHECK: OpBranch %[[#new_merge]]
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; CHECK: %[[#new_merge]] = OpLabel
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; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#switch_0]]
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; CHECK: %[[#cond:]] = OpIEqual %[[#]] %[[#int_0]] %[[#tmp]]
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; CHECK: OpBranchConditional %[[#cond]] %[[#merge]] %[[#br_true:]]
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; CHECK: %[[#br_true]] = OpLabel
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; CHECK: OpBranch %[[#merge]]
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; CHECK: %[[#merge]] = OpLabel
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; CHECK: OpReturn
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%var = alloca i32, align 4
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br i1 true, label %br_true, label %br_false
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br_false:
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store i32 0, ptr %var, align 4
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br i1 true, label %br_true, label %merge
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br_true:
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store i32 0, ptr %var, align 4
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br label %merge
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merge:
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ret void
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}
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declare token @llvm.experimental.convergence.entry() #2
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attributes #0 = { convergent noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #2 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #3 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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!llvm.module.flags = !{!0, !1, !2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
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!2 = !{i32 7, !"frame-pointer", i32 2}
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