derek.holloway
7502bf64a4
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47 lines
1.5 KiB
LLVM
47 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; Test complex addresses with base or index truncated from 128 bit.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Shift amount with base truncated from 128 bit to 32 bit.
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define void @f1(i128 %x, i32 %y, ptr %px, ptr %py) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: larl %r1, .LCPI0_0
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; CHECK-NEXT: vl %v0, 0(%r2), 3
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; CHECK-NEXT: vl %v1, 0(%r1), 3
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; CHECK-NEXT: vaq %v0, %v0, %v1
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; CHECK-NEXT: vlgvf %r1, %v0, 3
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; CHECK-NEXT: srl %r3, 0(%r1)
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; CHECK-NEXT: vst %v0, 0(%r4), 3
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; CHECK-NEXT: st %r3, 0(%r5)
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; CHECK-NEXT: br %r14
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%x1 = add i128 %x, 1
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store i128 %x1, ptr %px, align 8
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%amt = trunc i128 %x1 to i32
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%y1 = lshr i32 %y, %amt
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store i32 %y1, ptr %py, align 4
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ret void
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}
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; Memory address with index truncated from 128 bit to 64 bit.
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define i8 @f2(ptr %base, ptr %p) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: larl %r1, .LCPI1_0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r1), 3
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; CHECK-NEXT: vaq %v0, %v0, %v1
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; CHECK-NEXT: vlgvg %r1, %v0, 1
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; CHECK-NEXT: vst %v0, 0(%r3), 3
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; CHECK-NEXT: lb %r2, 0(%r1,%r2)
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; CHECK-NEXT: br %r14
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%idx = load i128, ptr %p, align 8
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%inc = add nsw i128 %idx, 1
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store i128 %inc, ptr %p, align 8
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%idxprom = trunc i128 %inc to i64
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%arrayidx = getelementptr inbounds i8, ptr %base, i64 %idxprom
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%res = load i8, ptr %arrayidx, align 1
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ret i8 %res
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}
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