derek.holloway
7502bf64a4
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204 lines
6.2 KiB
YAML
204 lines
6.2 KiB
YAML
# RUN: llc -mtriple=s390x-linux-gnu -start-before=prologepilog %s -o - -mcpu=z14 \
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# RUN: -debug-only=prologepilog -print-after=prologepilog -verify-machineinstrs 2>&1 \
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# RUN: | FileCheck %s
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# REQUIRES: asserts
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#
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# Test that stack objects are ordered in a good way with respect to the
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# displacement operands of users.
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--- |
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define void @f1() { ret void }
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define void @f2() { ret void }
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define void @f3() { ret void }
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define void @f4() { ret void }
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define void @f5() { ret void }
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define void @f6() { ret void }
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...
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### Test that %stack.0 is placed close to its D12 user.
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# CHECK: alloc FI(1) at SP[-4255]
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# CHECK-NEXT: alloc FI(0) at SP[-4271]
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# CHECK-NEXT: alloc FI(2) at SP[-4280]
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# CHECK-NEXT: alloc FI(3) at SP[-4288]
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# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
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# CHECK-NEXT: # Machine code for function f1: IsSSA, NoPHIs, TracksLiveness, NoVRegs
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# CHECK-NOT: LAY
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# CHECK: VL32
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---
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name: f1
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 16 }
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- { id: 1, size: 4095 }
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machineFunctionInfo: {}
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body: |
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bb.0:
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renamable $f0s = VL32 %stack.0, 0, $noreg
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Return
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...
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### Test that %stack.1 is placed close to its D12 user.
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# CHECK: alloc FI(0) at SP[-176]
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# CHECK-NEXT: alloc FI(1) at SP[-4271]
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# CHECK-NEXT: alloc FI(2) at SP[-4280]
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# CHECK-NEXT: alloc FI(3) at SP[-4288]
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# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
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# CHECK-NEXT: # Machine code for function f2: IsSSA, NoPHIs, TracksLiveness, NoVRegs
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# CHECK-NOT: LAY
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# CHECK: VL32
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---
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name: f2
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 16 }
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- { id: 1, size: 4095 }
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machineFunctionInfo: {}
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body: |
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bb.0:
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renamable $f0s = VL32 %stack.1, 3916, $noreg
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Return
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...
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### Swap the order of the objects so that both accesses are in range.
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# CHECK: alloc FI(1) at SP[-8350]
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# CHECK-NEXT: alloc FI(0) at SP[-12445]
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# CHECK-NEXT: alloc FI(2) at SP[-12456]
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# CHECK-NEXT: alloc FI(3) at SP[-12464]
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# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
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# CHECK-NEXT: # Machine code for function f3: IsSSA, NoPHIs, TracksLiveness, NoVRegs
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# CHECK-NOT: LAY
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# CHECK: VL32
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# CHECK-NOT: LAY
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# CHECK: LEY
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---
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name: f3
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 4095 }
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- { id: 1, size: 8190 }
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machineFunctionInfo: {}
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body: |
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bb.0:
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renamable $f0s = VL32 %stack.0, 0, $noreg
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renamable $f0s = LE %stack.1, 0, $noreg
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Return
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...
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### Reorder the objects so that all accesses are in range.
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# CHECK: alloc FI(0) at SP[-8350]
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# CHECK-NEXT: alloc FI(2) at SP[-16540]
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# CHECK-NEXT: alloc FI(3) at SP[-24730]
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# CHECK-NEXT: alloc FI(1) at SP[-26777]
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# CHECK-NEXT: alloc FI(4) at SP[-28824]
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# CHECK-NEXT: alloc FI(5) at SP[-28832]
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# CHECK-NEXT: alloc FI(6) at SP[-28840]
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# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
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# CHECK-NEXT: # Machine code for function f4: IsSSA, NoPHIs, TracksLiveness, NoVRegs
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# CHECK-NOT: LAY
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# CHECK: LEY
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# CHECK-NEXT: VL32
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# CHECK-NEXT: LEY
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# CHECK-NEXT: LEY
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# CHECK-NEXT: VL32
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---
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name: f4
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 8190 }
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- { id: 1, size: 2047 }
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- { id: 2, size: 8190 }
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- { id: 3, size: 8190 }
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- { id: 4, size: 2047 }
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machineFunctionInfo: {}
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body: |
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bb.0:
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renamable $f2s = LE %stack.0, 0, $noreg
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renamable $f0s = VL32 %stack.1, 0, $noreg
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renamable $f3s = LEY %stack.2, 0, $noreg
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renamable $f4s = LE %stack.3, 0, $noreg
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renamable $f1s = VL32 %stack.4, 0, $noreg
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Return
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...
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### Reorder the objects so that the VL32 object is in range and the LYs are
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### shortened to Ls (STOC cannot be shortened).
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# CHECK: alloc FI(0) at SP[-8350]
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# CHECK-NEXT: alloc FI(1) at SP[-16540]
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# CHECK-NEXT: alloc FI(2) at SP[-24730]
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# CHECK-NEXT: alloc FI(3) at SP[-26777]
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# CHECK-NEXT: alloc FI(4) at SP[-26792]
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# CHECK-NEXT: alloc FI(5) at SP[-26800]
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# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
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# CHECK-NEXT: # Machine code for function f5: IsSSA, NoPHIs, TracksLiveness, NoVRegs
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# CHECK-NOT: LAY
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# CHECK: $r1l = L $r15
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# CHECK-NEXT: $r1l = L $r15
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# CHECK-NEXT: IMPLICIT_DEF
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# CHECK-NEXT: STOC
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# CHECK-NEXT: STOC
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# CHECK-NEXT: VL32
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---
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name: f5
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 8190 }
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- { id: 1, size: 8190 }
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- { id: 2, size: 8190 }
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- { id: 3, size: 2047 }
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machineFunctionInfo: {}
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body: |
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bb.0:
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$r1l = LY %stack.2, 0, $noreg
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$r1l = LY %stack.2, 0, $noreg
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$cc = IMPLICIT_DEF
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STOC $r1l, %stack.0, 0, 14, 8, implicit $cc
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STOC $r1l, %stack.1, 0, 14, 8, implicit $cc
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renamable $f3s = VL32 %stack.3, 0, $noreg
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Return
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...
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### Test handling of a variable sized object.
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# CHECK: alloc FI(1) at SP[-476]
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# CHECK-NEXT: alloc FI(0) at SP[-776]
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# CHECK-NEXT: alloc FI(2) at SP[-776]
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# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
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# CHECK-NEXT: # Machine code for function f6: IsSSA, NoPHIs, TracksLiveness, NoVRegs
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# CHECK: $r15d = AGHI $r15d(tied-def 0), -776, implicit-def dead $cc
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# CHECK: $r11d = LGR $r15d
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# CHECK: renamable $r2d = ADJDYNALLOC renamable $r1d, 0, $noreg
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# CHECK: VST64 renamable $f0d, $r11d, 160, $noreg
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# CHECK: VST32 renamable $f1s, $r11d, 460, $noreg
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# CHECK: VST32 killed renamable $f0s, killed renamable $r2d, 0, $noreg
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---
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name: f6
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tracksRegLiveness: true
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stack:
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- { id: 0, size: 300 }
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- { id: 1, size: 316 }
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- { id: 2, type: variable-sized }
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $f0d, $f0s, $f1s, $r2l
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renamable $r2l = KILL $r2l, implicit-def $r2d
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renamable $r1d = RISBGN undef renamable $r1d, killed renamable $r2d, 30, 189, 2
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renamable $r0d = nuw LA killed renamable $r1d, 7, $noreg
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renamable $r0d = RISBGN undef renamable $r0d, killed renamable $r0d, 29, 188, 0
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renamable $r1d = SGRK $r15d, killed renamable $r0d, implicit-def dead $cc
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renamable $r2d = ADJDYNALLOC renamable $r1d, 0, $noreg
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$r15d = COPY killed renamable $r1d
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VST64 renamable $f0d, %stack.0, 0, $noreg
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VST32 renamable $f1s, %stack.1, 0, $noreg
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VST32 killed renamable $f0s, killed renamable $r2d, 0, $noreg
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Return
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...
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