derek.holloway
7502bf64a4
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32 lines
1.1 KiB
YAML
32 lines
1.1 KiB
YAML
# Check that the extra operand for the full register added by RegAlloc does
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# not have a latency that interferes with the latency adjustment
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# (ReadAdvance) for the MSY register operand.
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# RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=machine-scheduler \
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# RUN: -debug-only=machine-scheduler -o - 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# CHECK: ScheduleDAGMI::schedule starting
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# CHECK: SU(4): renamable $r2l = MSR renamable $r2l(tied-def 0), renamable $r2l
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# CHECK: Latency : 6
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# CHECK: SU(5): renamable $r2l = MSY renamable $r2l(tied-def 0), renamable $r1d, -4, $noreg, implicit $r2d
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# CHECK: Predecessors:
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# CHECK: SU(4): Data Latency=2 Reg=$r2l
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# CHECK: SU(4): Data Latency=0 Reg=$r2d
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---
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name: Perl_do_sv_dump
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0 :
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%1:addr64bit = IMPLICIT_DEF
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%2:addr64bit = IMPLICIT_DEF
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%3:vr64bit = IMPLICIT_DEF
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bb.1 :
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%2:addr64bit = ALGFI %2, 4294967291, implicit-def dead $cc
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%2.subreg_l32:addr64bit = MSR %2.subreg_l32, %2.subreg_l32
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%2.subreg_l32:addr64bit = MSY %2.subreg_l32, %1, -4, $noreg
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...
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