derek.holloway
7502bf64a4
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114 lines
2.9 KiB
LLVM
114 lines
2.9 KiB
LLVM
; Test vector zero extensions, which need to be implemented as ANDs.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a v16i1->v16i8 extension.
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define <16 x i8> @f1(<16 x i8> %val) {
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; CHECK-LABEL: f1:
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; CHECK: vrepib [[REG:%v[0-9]+]], 1
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <16 x i8> %val to <16 x i1>
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%ret = zext <16 x i1> %trunc to <16 x i8>
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ret <16 x i8> %ret
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}
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; Test a v8i1->v8i16 extension.
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define <8 x i16> @f2(<8 x i16> %val) {
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; CHECK-LABEL: f2:
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; CHECK: vrepih [[REG:%v[0-9]+]], 1
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <8 x i16> %val to <8 x i1>
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%ret = zext <8 x i1> %trunc to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test a v8i8->v8i16 extension.
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define <8 x i16> @f3(<8 x i16> %val) {
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; CHECK-LABEL: f3:
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; CHECK: vgbm [[REG:%v[0-9]+]], 21845
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <8 x i16> %val to <8 x i8>
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%ret = zext <8 x i8> %trunc to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test a v4i1->v4i32 extension.
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define <4 x i32> @f4(<4 x i32> %val) {
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; CHECK-LABEL: f4:
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; CHECK: vrepif [[REG:%v[0-9]+]], 1
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <4 x i32> %val to <4 x i1>
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%ret = zext <4 x i1> %trunc to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test a v4i8->v4i32 extension.
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define <4 x i32> @f5(<4 x i32> %val) {
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; CHECK-LABEL: f5:
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; CHECK: vgbm [[REG:%v[0-9]+]], 4369
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <4 x i32> %val to <4 x i8>
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%ret = zext <4 x i8> %trunc to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test a v4i16->v4i32 extension.
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define <4 x i32> @f6(<4 x i32> %val) {
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; CHECK-LABEL: f6:
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; CHECK: vgbm [[REG:%v[0-9]+]], 13107
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <4 x i32> %val to <4 x i16>
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%ret = zext <4 x i16> %trunc to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test a v2i1->v2i64 extension.
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define <2 x i64> @f7(<2 x i64> %val) {
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; CHECK-LABEL: f7:
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; CHECK: vrepig [[REG:%v[0-9]+]], 1
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <2 x i64> %val to <2 x i1>
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%ret = zext <2 x i1> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test a v2i8->v2i64 extension.
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define <2 x i64> @f8(<2 x i64> %val) {
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; CHECK-LABEL: f8:
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; CHECK: vgbm [[REG:%v[0-9]+]], 257
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <2 x i64> %val to <2 x i8>
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%ret = zext <2 x i8> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test a v2i16->v2i64 extension.
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define <2 x i64> @f9(<2 x i64> %val) {
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; CHECK-LABEL: f9:
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; CHECK: vgbm [[REG:%v[0-9]+]], 771
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <2 x i64> %val to <2 x i16>
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%ret = zext <2 x i16> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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; Test a v2i32->v2i64 extension.
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define <2 x i64> @f10(<2 x i64> %val) {
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; CHECK-LABEL: f10:
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; CHECK: vgbm [[REG:%v[0-9]+]], 3855
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; CHECK: vn %v24, %v24, [[REG]]
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; CHECK: br %r14
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%trunc = trunc <2 x i64> %val to <2 x i32>
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%ret = zext <2 x i32> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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