derek.holloway
7502bf64a4
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101 lines
3.6 KiB
LLVM
101 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Test high-part vector multiply-and-add.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a v16i8 unsigned high-part multiply-and-add.
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define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmalhb %v24, %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%zext1 = zext <16 x i8> %val1 to <16 x i16>
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%zext2 = zext <16 x i8> %val2 to <16 x i16>
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%zext3 = zext <16 x i8> %val3 to <16 x i16>
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%mulx = mul <16 x i16> %zext1, %zext2
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%addx = add <16 x i16> %mulx, %zext3
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%highx = lshr <16 x i16> %addx, splat(i16 8)
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%high = trunc <16 x i16> %highx to <16 x i8>
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ret <16 x i8> %high
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}
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; Test a v16i8 signed high-part multiply-and-add.
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define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmahb %v24, %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%sext1 = sext <16 x i8> %val1 to <16 x i16>
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%sext2 = sext <16 x i8> %val2 to <16 x i16>
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%sext3 = sext <16 x i8> %val3 to <16 x i16>
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%mulx = mul <16 x i16> %sext1, %sext2
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%addx = add <16 x i16> %mulx, %sext3
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%highx = lshr <16 x i16> %addx, splat(i16 8)
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%high = trunc <16 x i16> %highx to <16 x i8>
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ret <16 x i8> %high
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}
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; Test a v8i16 unsigned high-part multiply-and-add.
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define <8 x i16> @f3(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmalhh %v24, %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%zext1 = zext <8 x i16> %val1 to <8 x i32>
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%zext2 = zext <8 x i16> %val2 to <8 x i32>
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%zext3 = zext <8 x i16> %val3 to <8 x i32>
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%mulx = mul <8 x i32> %zext1, %zext2
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%addx = add <8 x i32> %mulx, %zext3
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%highx = lshr <8 x i32> %addx, splat(i32 16)
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%high = trunc <8 x i32> %highx to <8 x i16>
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ret <8 x i16> %high
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}
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; Test a v8i16 signed high-part multiply-and-add.
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define <8 x i16> @f4(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmahh %v24, %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%sext1 = sext <8 x i16> %val1 to <8 x i32>
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%sext2 = sext <8 x i16> %val2 to <8 x i32>
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%sext3 = sext <8 x i16> %val3 to <8 x i32>
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%mulx = mul <8 x i32> %sext1, %sext2
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%addx = add <8 x i32> %mulx, %sext3
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%highx = lshr <8 x i32> %addx, splat(i32 16)
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%high = trunc <8 x i32> %highx to <8 x i16>
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ret <8 x i16> %high
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}
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; Test a v4i32 unsigned high-part multiply-and-add.
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define <4 x i32> @f5(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmalhf %v24, %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%zext1 = zext <4 x i32> %val1 to <4 x i64>
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%zext2 = zext <4 x i32> %val2 to <4 x i64>
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%zext3 = zext <4 x i32> %val3 to <4 x i64>
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%mulx = mul <4 x i64> %zext1, %zext2
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%addx = add <4 x i64> %mulx, %zext3
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%highx = lshr <4 x i64> %addx, splat(i64 32)
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%high = trunc <4 x i64> %highx to <4 x i32>
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ret <4 x i32> %high
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}
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; Test a v4i32 signed high-part multiply-and-add.
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define <4 x i32> @f6(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmahf %v24, %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%sext1 = sext <4 x i32> %val1 to <4 x i64>
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%sext2 = sext <4 x i32> %val2 to <4 x i64>
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%sext3 = sext <4 x i32> %val3 to <4 x i64>
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%mulx = mul <4 x i64> %sext1, %sext2
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%addx = add <4 x i64> %mulx, %sext3
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%highx = lshr <4 x i64> %addx, splat(i64 32)
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%high = trunc <4 x i64> %highx to <4 x i32>
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ret <4 x i32> %high
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}
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