derek.holloway
7502bf64a4
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141 lines
5.0 KiB
LLVM
141 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i128:64-v128:64:128-a:0:64-n64-S64"
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target triple = "thumbv6---gnueabi"
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; Function Attrs: norecurse nounwind readonly
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define i128 @a(ptr nocapture readonly %z) {
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; CHECK-LABEL: a:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: .pad #28
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; CHECK-NEXT: sub sp, #28
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; CHECK-NEXT: ldr r1, [r0, #32]
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; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
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; CHECK-NEXT: ldr r1, [r0, #36]
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; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill
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; CHECK-NEXT: ldr r1, [r0, #40]
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; CHECK-NEXT: str r1, [sp, #24] @ 4-byte Spill
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; CHECK-NEXT: ldr r3, [r0, #44]
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; CHECK-NEXT: ldr r6, [r0]
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; CHECK-NEXT: str r6, [sp, #4] @ 4-byte Spill
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; CHECK-NEXT: adds r5, r0, #4
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; CHECK-NEXT: ldm r5, {r1, r2, r4, r5}
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; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
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; CHECK-NEXT: ldr r5, [r0, #20]
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; CHECK-NEXT: str r5, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: ldr r7, [r0, #24]
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; CHECK-NEXT: ldr r5, [r0, #28]
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; CHECK-NEXT: adds r0, r2, r6
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: adcs r0, r1
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; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
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; CHECK-NEXT: ldr r6, [sp, #24] @ 4-byte Reload
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; CHECK-NEXT: adcs r6, r0
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; CHECK-NEXT: str r6, [sp, #24] @ 4-byte Spill
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; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
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; CHECK-NEXT: adcs r3, r0
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; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
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; CHECK-NEXT: adds r6, r2, r0
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; CHECK-NEXT: adcs r4, r1
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; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
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; CHECK-NEXT: adcs r7, r0
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; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: adcs r5, r0
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; CHECK-NEXT: mov r0, r6
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; CHECK-NEXT: mov r1, r4
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; CHECK-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
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; CHECK-NEXT: bl __aeabi_lmul
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; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
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; CHECK-NEXT: str r1, [sp, #24] @ 4-byte Spill
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; CHECK-NEXT: mov r0, r7
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; CHECK-NEXT: mov r1, r5
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; CHECK-NEXT: mov r2, r6
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; CHECK-NEXT: mov r3, r4
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; CHECK-NEXT: bl __aeabi_lmul
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; CHECK-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
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; CHECK-NEXT: adds r0, r0, r2
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; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
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; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
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; CHECK-NEXT: adcs r0, r1
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; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
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; CHECK-NEXT: movs r7, #0
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: mov r1, r7
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; CHECK-NEXT: mov r2, r6
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; CHECK-NEXT: mov r3, r7
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; CHECK-NEXT: bl __aeabi_lmul
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: mov r5, r1
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; CHECK-NEXT: mov r0, r6
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; CHECK-NEXT: mov r1, r7
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; CHECK-NEXT: mov r2, r6
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; CHECK-NEXT: mov r3, r7
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; CHECK-NEXT: bl __aeabi_lmul
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; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill
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; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: adds r0, r0, r1
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: adcs r5, r7
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; CHECK-NEXT: mov r0, r6
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; CHECK-NEXT: mov r1, r7
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; CHECK-NEXT: mov r2, r4
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; CHECK-NEXT: mov r3, r7
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; CHECK-NEXT: bl __aeabi_lmul
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; CHECK-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: adds r0, r0, r2
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: adcs r1, r7
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; CHECK-NEXT: adds r6, r5, r1
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; CHECK-NEXT: mov r5, r7
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; CHECK-NEXT: adcs r5, r7
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; CHECK-NEXT: mov r0, r4
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; CHECK-NEXT: mov r1, r7
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; CHECK-NEXT: mov r2, r4
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; CHECK-NEXT: mov r3, r7
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; CHECK-NEXT: bl __aeabi_lmul
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; CHECK-NEXT: adds r0, r0, r6
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; CHECK-NEXT: adcs r5, r1
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; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
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; CHECK-NEXT: adds r2, r0, r1
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; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
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; CHECK-NEXT: adcs r5, r0
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; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
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; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: mov r3, r5
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; CHECK-NEXT: add sp, #28
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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entry:
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%0 = load i64, ptr %z, align 4
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%conv.i = zext i64 %0 to i128
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%arrayidx1 = getelementptr inbounds i64, ptr %z, i64 2
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%1 = load i64, ptr %arrayidx1, align 4
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%conv.i38 = zext i64 %1 to i128
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%shl.i39 = shl nuw i128 %conv.i38, 64
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%or = or i128 %shl.i39, %conv.i
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%arrayidx3 = getelementptr inbounds i64, ptr %z, i64 1
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%2 = load i64, ptr %arrayidx3, align 4
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%conv.i37 = zext i64 %2 to i128
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%arrayidx5 = getelementptr inbounds i64, ptr %z, i64 3
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%3 = load i64, ptr %arrayidx5, align 4
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%conv.i35 = zext i64 %3 to i128
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%shl.i36 = shl nuw i128 %conv.i35, 64
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%or7 = or i128 %shl.i36, %conv.i37
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%arrayidx10 = getelementptr inbounds i64, ptr %z, i64 4
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%4 = load i64, ptr %arrayidx10, align 4
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%conv.i64 = zext i64 %4 to i128
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%shl.i33 = shl nuw i128 %conv.i64, 64
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%or12 = or i128 %shl.i33, %conv.i
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%arrayidx15 = getelementptr inbounds i64, ptr %z, i64 5
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%5 = load i64, ptr %arrayidx15, align 4
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%conv.i30 = zext i64 %5 to i128
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%shl.i = shl nuw i128 %conv.i30, 64
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%or17 = or i128 %shl.i, %conv.i37
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%add = add i128 %or7, %or
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%add18 = add i128 %or17, %or12
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%mul = mul i128 %add18, %add
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ret i128 %mul
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}
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