derek.holloway
7502bf64a4
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296 lines
8.7 KiB
LLVM
296 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv6m-none-unknown-eabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=ARM
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declare i4 @llvm.umul.fix.i4 (i4, i4, i32)
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declare i32 @llvm.umul.fix.i32 (i32, i32, i32)
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declare i64 @llvm.umul.fix.i64 (i64, i64, i32)
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define i32 @func(i32 %x, i32 %y) nounwind {
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; ARM-LABEL: func:
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; ARM: @ %bb.0:
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; ARM-NEXT: .save {r7, lr}
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; ARM-NEXT: push {r7, lr}
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; ARM-NEXT: mov r2, r1
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; ARM-NEXT: movs r1, #0
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; ARM-NEXT: mov r3, r1
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: lsrs r0, r0, #2
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; ARM-NEXT: lsls r1, r1, #30
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; ARM-NEXT: adds r0, r1, r0
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; ARM-NEXT: pop {r7, pc}
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%tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 2)
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ret i32 %tmp
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}
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define i64 @func2(i64 %x, i64 %y) nounwind {
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; ARM-LABEL: func2:
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; ARM: @ %bb.0:
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; ARM-NEXT: .save {r4, r5, r6, r7, lr}
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; ARM-NEXT: push {r4, r5, r6, r7, lr}
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; ARM-NEXT: .pad #20
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; ARM-NEXT: sub sp, #20
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; ARM-NEXT: str r3, [sp, #12] @ 4-byte Spill
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; ARM-NEXT: mov r4, r2
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; ARM-NEXT: mov r6, r1
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; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
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; ARM-NEXT: mov r5, r0
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; ARM-NEXT: movs r7, #0
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; ARM-NEXT: mov r1, r7
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; ARM-NEXT: mov r3, r7
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
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; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
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; ARM-NEXT: mov r0, r6
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; ARM-NEXT: mov r1, r7
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; ARM-NEXT: mov r2, r4
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; ARM-NEXT: mov r3, r7
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: mov r4, r1
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; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
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; ARM-NEXT: adds r0, r0, r1
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; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
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; ARM-NEXT: adcs r4, r7
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; ARM-NEXT: mov r0, r5
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; ARM-NEXT: mov r1, r7
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; ARM-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
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; ARM-NEXT: mov r2, r6
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; ARM-NEXT: mov r3, r7
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: mov r5, r1
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; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
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; ARM-NEXT: adds r0, r0, r1
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; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
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; ARM-NEXT: adcs r5, r4
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; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
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; ARM-NEXT: mov r1, r7
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; ARM-NEXT: mov r2, r6
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; ARM-NEXT: mov r3, r7
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: adds r0, r0, r5
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; ARM-NEXT: lsls r0, r0, #30
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; ARM-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
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; ARM-NEXT: lsrs r1, r2, #2
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; ARM-NEXT: adds r1, r0, r1
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; ARM-NEXT: lsls r0, r2, #30
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; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
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; ARM-NEXT: lsrs r2, r2, #2
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; ARM-NEXT: adds r0, r0, r2
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; ARM-NEXT: add sp, #20
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; ARM-NEXT: pop {r4, r5, r6, r7, pc}
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%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 2)
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ret i64 %tmp
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; ARM-LABEL: func3:
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; ARM: @ %bb.0:
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; ARM-NEXT: .save {r7, lr}
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; ARM-NEXT: push {r7, lr}
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; ARM-NEXT: movs r2, #15
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; ARM-NEXT: ands r0, r2
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; ARM-NEXT: ands r2, r1
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; ARM-NEXT: movs r1, #0
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; ARM-NEXT: mov r3, r1
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: lsrs r0, r0, #2
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; ARM-NEXT: lsls r1, r1, #30
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; ARM-NEXT: adds r0, r1, r0
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; ARM-NEXT: pop {r7, pc}
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%tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 2)
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ret i4 %tmp
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}
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;; These result in regular integer multiplication
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define i32 @func4(i32 %x, i32 %y) nounwind {
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; ARM-LABEL: func4:
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; ARM: @ %bb.0:
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; ARM-NEXT: muls r0, r1, r0
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; ARM-NEXT: bx lr
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%tmp = call i32 @llvm.umul.fix.i32(i32 %x, i32 %y, i32 0)
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ret i32 %tmp
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}
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define i64 @func5(i64 %x, i64 %y) nounwind {
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; ARM-LABEL: func5:
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; ARM: @ %bb.0:
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; ARM-NEXT: .save {r7, lr}
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; ARM-NEXT: push {r7, lr}
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: pop {r7, pc}
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%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 0)
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ret i64 %tmp
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}
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define i4 @func6(i4 %x, i4 %y) nounwind {
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; ARM-LABEL: func6:
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; ARM: @ %bb.0:
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; ARM-NEXT: movs r2, #15
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; ARM-NEXT: ands r1, r2
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; ARM-NEXT: ands r0, r2
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; ARM-NEXT: muls r0, r1, r0
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; ARM-NEXT: bx lr
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%tmp = call i4 @llvm.umul.fix.i4(i4 %x, i4 %y, i32 0)
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ret i4 %tmp
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}
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define i64 @func7(i64 %x, i64 %y) nounwind {
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; ARM-LABEL: func7:
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; ARM: @ %bb.0:
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; ARM-NEXT: .save {r4, r5, r6, r7, lr}
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; ARM-NEXT: push {r4, r5, r6, r7, lr}
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; ARM-NEXT: .pad #12
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; ARM-NEXT: sub sp, #12
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; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill
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; ARM-NEXT: mov r4, r2
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; ARM-NEXT: mov r5, r1
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; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
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; ARM-NEXT: mov r7, r0
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; ARM-NEXT: movs r6, #0
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: str r1, [sp] @ 4-byte Spill
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; ARM-NEXT: mov r0, r5
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: mov r2, r4
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: mov r4, r1
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; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
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; ARM-NEXT: adds r0, r0, r1
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; ARM-NEXT: str r0, [sp] @ 4-byte Spill
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; ARM-NEXT: adcs r4, r6
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; ARM-NEXT: mov r0, r7
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
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; ARM-NEXT: mov r2, r7
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: mov r5, r1
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; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
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; ARM-NEXT: adds r0, r0, r1
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; ARM-NEXT: str r0, [sp] @ 4-byte Spill
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; ARM-NEXT: adcs r5, r4
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; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: mov r2, r7
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: adds r1, r0, r5
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; ARM-NEXT: ldr r0, [sp] @ 4-byte Reload
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; ARM-NEXT: add sp, #12
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; ARM-NEXT: pop {r4, r5, r6, r7, pc}
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%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 32)
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ret i64 %tmp
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}
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define i64 @func8(i64 %x, i64 %y) nounwind {
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; ARM-LABEL: func8:
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; ARM: @ %bb.0:
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; ARM-NEXT: .save {r4, r5, r6, r7, lr}
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; ARM-NEXT: push {r4, r5, r6, r7, lr}
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; ARM-NEXT: .pad #12
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; ARM-NEXT: sub sp, #12
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; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill
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; ARM-NEXT: mov r4, r2
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; ARM-NEXT: mov r5, r1
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; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
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; ARM-NEXT: mov r7, r0
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; ARM-NEXT: movs r6, #0
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: str r1, [sp] @ 4-byte Spill
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; ARM-NEXT: mov r0, r5
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: mov r2, r4
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: mov r4, r1
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; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
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; ARM-NEXT: adds r0, r0, r1
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; ARM-NEXT: str r0, [sp] @ 4-byte Spill
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; ARM-NEXT: adcs r4, r6
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; ARM-NEXT: mov r0, r7
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
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; ARM-NEXT: mov r2, r5
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: ldr r2, [sp] @ 4-byte Reload
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; ARM-NEXT: adds r0, r0, r2
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; ARM-NEXT: str r0, [sp] @ 4-byte Spill
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; ARM-NEXT: adcs r1, r6
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; ARM-NEXT: adds r4, r4, r1
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; ARM-NEXT: mov r7, r6
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; ARM-NEXT: adcs r7, r6
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; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: mov r2, r5
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: adds r0, r0, r4
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; ARM-NEXT: adcs r1, r7
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; ARM-NEXT: lsls r1, r1, #1
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; ARM-NEXT: lsrs r2, r0, #31
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; ARM-NEXT: adds r1, r1, r2
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; ARM-NEXT: lsls r0, r0, #1
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; ARM-NEXT: ldr r2, [sp] @ 4-byte Reload
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; ARM-NEXT: lsrs r2, r2, #31
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; ARM-NEXT: adds r0, r0, r2
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; ARM-NEXT: add sp, #12
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; ARM-NEXT: pop {r4, r5, r6, r7, pc}
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%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 63)
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ret i64 %tmp
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}
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define i64 @func9(i64 %x, i64 %y) nounwind {
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; ARM-LABEL: func9:
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; ARM: @ %bb.0:
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; ARM-NEXT: .save {r4, r5, r6, r7, lr}
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; ARM-NEXT: push {r4, r5, r6, r7, lr}
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; ARM-NEXT: .pad #12
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; ARM-NEXT: sub sp, #12
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; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill
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; ARM-NEXT: mov r4, r2
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; ARM-NEXT: mov r5, r1
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; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
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; ARM-NEXT: mov r7, r0
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; ARM-NEXT: movs r6, #0
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: str r1, [sp] @ 4-byte Spill
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; ARM-NEXT: mov r0, r5
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: mov r2, r4
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: mov r4, r1
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; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
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; ARM-NEXT: adds r5, r0, r1
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; ARM-NEXT: adcs r4, r6
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; ARM-NEXT: mov r0, r7
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
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; ARM-NEXT: mov r2, r7
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: adds r0, r0, r5
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; ARM-NEXT: adcs r1, r6
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; ARM-NEXT: adds r4, r4, r1
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; ARM-NEXT: mov r5, r6
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; ARM-NEXT: adcs r5, r6
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; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
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; ARM-NEXT: mov r1, r6
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; ARM-NEXT: mov r2, r7
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; ARM-NEXT: mov r3, r6
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; ARM-NEXT: bl __aeabi_lmul
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; ARM-NEXT: adds r0, r0, r4
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; ARM-NEXT: adcs r1, r5
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; ARM-NEXT: add sp, #12
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; ARM-NEXT: pop {r4, r5, r6, r7, pc}
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%tmp = call i64 @llvm.umul.fix.i64(i64 %x, i64 %y, i32 64)
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ret i64 %tmp
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}
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