TheRock/compiler/amd-llvm/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-known-bits.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -mtriple=thumbv8.1m.main -mve-tail-predication -tail-predication=enabled -mattr=+mve %s -S -o - | FileCheck %s

; Check that tail predication still triggers correctly when the back-edge taken
; count is known to be a multiple of 2.

; Function Attrs: nofree norecurse nosync nounwind memory(argmem: read)
define dso_local i32 @example(ptr noundef readonly captures(none) %ptr, i32 noundef %n) {
; CHECK-LABEL: define dso_local i32 @example(
; CHECK-SAME: ptr noundef readonly captures(none) [[PTR:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[N]], 0
; CHECK-NEXT:    br i1 [[CMP3]], label %[[FOR_BODY_PREHEADER:.*]], label %[[FOR_COND_CLEANUP:.*]]
; CHECK:       [[FOR_BODY_PREHEADER]]:
; CHECK-NEXT:    [[MUL:%.*]] = shl i32 [[N]], 1
; CHECK-NEXT:    [[N_RND_UP:%.*]] = add i32 [[MUL]], 14
; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N_RND_UP]], -16
; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[N_VEC]], -16
; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[TMP0]], 4
; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 1
; CHECK-NEXT:    [[TMP3:%.*]] = call i32 @llvm.start.loop.iterations.i32(i32 [[TMP2]])
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[VECTOR_BODY]] ], [ [[PTR]], %[[FOR_BODY_PREHEADER]] ]
; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi i32 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[TMP4:%.*]] = phi i32 [ [[TMP3]], %[[FOR_BODY_PREHEADER]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi i32 [ [[MUL]], %[[FOR_BODY_PREHEADER]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = call <16 x i1> @llvm.arm.mve.vctp8(i32 [[TMP5]])
; CHECK-NEXT:    [[TMP7]] = sub i32 [[TMP5]], 16
; CHECK-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 [[LSR_IV]], <16 x i1> [[TMP6]], <16 x i8> poison)
; CHECK-NEXT:    [[TMP8:%.*]] = zext <16 x i8> [[WIDE_MASKED_LOAD]] to <16 x i32>
; CHECK-NEXT:    [[TMP9:%.*]] = select <16 x i1> [[TMP6]], <16 x i32> [[TMP8]], <16 x i32> zeroinitializer
; CHECK-NEXT:    [[TMP10:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP9]])
; CHECK-NEXT:    [[TMP11]] = add i32 [[VEC_PHI]], [[TMP10]]
; CHECK-NEXT:    [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV]], i32 16
; CHECK-NEXT:    [[TMP12]] = call i32 @llvm.loop.decrement.reg.i32(i32 [[TMP4]], i32 1)
; CHECK-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
; CHECK-NEXT:    br i1 [[TMP13]], label %[[VECTOR_BODY]], label %[[FOR_COND_CLEANUP]]
; CHECK:       [[FOR_COND_CLEANUP]]:
; CHECK-NEXT:    [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[TMP11]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    ret i32 [[SUM_0_LCSSA]]
;
entry:
  %cmp3 = icmp sgt i32 %n, 0
  br i1 %cmp3, label %for.body.preheader, label %for.cond.cleanup

for.body.preheader:                               ; preds = %entry
  %mul = shl nuw i32 %n, 1
  %n.rnd.up = add i32 %mul, 14
  %n.vec = and i32 %n.rnd.up, -16
  %0 = add i32 %n.vec, -16
  %1 = lshr i32 %0, 4
  %2 = add nuw nsw i32 %1, 1
  %3 = call i32 @llvm.start.loop.iterations.i32(i32 %2)
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %for.body.preheader
  %lsr.iv = phi ptr [ %scevgep, %vector.body ], [ %ptr, %for.body.preheader ]
  %index = phi i32 [ 0, %for.body.preheader ], [ %index.next, %vector.body ]
  %vec.phi = phi i32 [ 0, %for.body.preheader ], [ %8, %vector.body ]
  %4 = phi i32 [ %3, %for.body.preheader ], [ %9, %vector.body ]
  %active.lane.mask = tail call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %mul)
  %wide.masked.load = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr align 1 %lsr.iv, <16 x i1> %active.lane.mask, <16 x i8> poison)
  %5 = zext <16 x i8> %wide.masked.load to <16 x i32>
  %6 = select <16 x i1> %active.lane.mask, <16 x i32> %5, <16 x i32> zeroinitializer
  %7 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)
  %8 = add i32 %vec.phi, %7
  %index.next = add i32 %index, 16
  %scevgep = getelementptr i8, ptr %lsr.iv, i32 16
  %9 = call i32 @llvm.loop.decrement.reg.i32(i32 %4, i32 1)
  %10 = icmp ne i32 %9, 0
  br i1 %10, label %vector.body, label %for.cond.cleanup

for.cond.cleanup:                                 ; preds = %vector.body, %entry
  %sum.0.lcssa = phi i32 [ 0, %entry ], [ %8, %vector.body ]
  ret i32 %sum.0.lcssa
}