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Flatten subprojects into a single base monorepo
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECKLE,CHECKLE-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECKLE,CHECKLE-MVEFP
; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECKBE
define arm_aapcs_vfpcc <16 x i8> @mov_int8_1() {
; CHECK-LABEL: mov_int8_1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 q0, #0x1
; CHECK-NEXT: bx lr
entry:
ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
}
define arm_aapcs_vfpcc <16 x i8> @xor_int8_1(<16 x i8> %a) {
; CHECKLE-LABEL: xor_int8_1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i8 q1, #0x1
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int8_1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i8 q1, #0x1
; CHECKBE-NEXT: vrev64.8 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %b
}
define arm_aapcs_vfpcc <16 x i8> @mov_int8_m1() {
; CHECK-LABEL: mov_int8_m1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 q0, #0xff
; CHECK-NEXT: bx lr
entry:
ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
}
define arm_aapcs_vfpcc <16 x i8> @xor_int8_m1(<16 x i8> %a) {
; CHECKLE-LABEL: xor_int8_m1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmvn q0, q0
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int8_m1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vrev64.8 q1, q0
; CHECKBE-NEXT: vmvn q1, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
ret <16 x i8> %b
}
; This has 0x01020304 or 0x04030201 vdup.32'd to q reg depending on endianness.
; The big endian is different as there is an implicit vrev64.8 out of the
; function, which gets constant folded away.
define arm_aapcs_vfpcc <16 x i8> @mov_int8_1234() {
; CHECKLE-LABEL: mov_int8_1234:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: movw r0, #513
; CHECKLE-NEXT: movt r0, #1027
; CHECKLE-NEXT: vdup.32 q0, r0
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: mov_int8_1234:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: movw r0, #772
; CHECKBE-NEXT: movt r0, #258
; CHECKBE-NEXT: vdup.32 q0, r0
; CHECKBE-NEXT: bx lr
entry:
ret <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>
}
define arm_aapcs_vfpcc <16 x i8> @xor_int8_1234(<16 x i8> %a) {
; CHECKLE-LABEL: xor_int8_1234:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: movw r0, #513
; CHECKLE-NEXT: movt r0, #1027
; CHECKLE-NEXT: vdup.32 q1, r0
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int8_1234:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: movw r0, #513
; CHECKBE-NEXT: vrev64.8 q1, q0
; CHECKBE-NEXT: movt r0, #1027
; CHECKBE-NEXT: vdup.32 q0, r0
; CHECKBE-NEXT: veor q1, q1, q0
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <16 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>
ret <16 x i8> %b
}
define arm_aapcs_vfpcc <16 x i8> @mov_int8_32() {
; CHECKLE-LABEL: mov_int8_32:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i32 q0, #0x1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: mov_int8_32:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i32 q0, #0x1000000
; CHECKBE-NEXT: bx lr
entry:
ret <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>
}
define arm_aapcs_vfpcc <16 x i8> @xor_int8_32(<16 x i8> %a) {
; CHECKLE-LABEL: xor_int8_32:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i32 q1, #0x1
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int8_32:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i32 q1, #0x1
; CHECKBE-NEXT: vrev64.8 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <16 x i8> %a, <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>
ret <16 x i8> %b
}
define arm_aapcs_vfpcc <16 x i8> @mov_int8_64() {
; CHECKLE-LABEL: mov_int8_64:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q0, #0xffff00ffff0000ff
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: mov_int8_64:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q0, #0xff0000ffff00ffff
; CHECKBE-NEXT: bx lr
entry:
ret <16 x i8> <i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255>
}
define arm_aapcs_vfpcc <16 x i8> @xor_int8_64(<16 x i8> %a) {
; CHECKLE-LABEL: xor_int8_64:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q1, #0xffff00ffff0000ff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int8_64:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xffff00ffff0000ff
; CHECKBE-NEXT: vrev64.8 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <16 x i8> %a, <i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255>
ret <16 x i8> %b
}
define arm_aapcs_vfpcc <8 x i16> @mov_int16_1() {
; CHECK-LABEL: mov_int16_1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i16 q0, #0x1
; CHECK-NEXT: bx lr
entry:
ret <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
}
define arm_aapcs_vfpcc <8 x i16> @xor_int16_1(<8 x i16> %a) {
; CHECKLE-LABEL: xor_int16_1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i16 q1, #0x1
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int16_1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i16 q1, #0x1
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %b
}
define arm_aapcs_vfpcc <8 x i16> @mov_int16_m1() {
; CHECK-LABEL: mov_int16_m1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 q0, #0xff
; CHECK-NEXT: bx lr
entry:
ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
}
define arm_aapcs_vfpcc <8 x i16> @xor_int16_m1(<8 x i16> %a) {
; CHECKLE-LABEL: xor_int16_m1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmvn q0, q0
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int16_m1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i8 q1, #0xff
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
ret <8 x i16> %b
}
define arm_aapcs_vfpcc <8 x i16> @mov_int16_256() {
; CHECK-LABEL: mov_int16_256:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i16 q0, #0x100
; CHECK-NEXT: bx lr
entry:
ret <8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
}
define arm_aapcs_vfpcc <8 x i16> @xor_int16_256(<8 x i16> %a) {
; CHECKLE-LABEL: xor_int16_256:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i16 q1, #0x100
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int16_256:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i16 q1, #0x100
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <8 x i16> %a, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
ret <8 x i16> %b
}
define arm_aapcs_vfpcc <8 x i16> @mov_int16_257() {
; CHECK-LABEL: mov_int16_257:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 q0, #0x1
; CHECK-NEXT: bx lr
entry:
ret <8 x i16> <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
}
define arm_aapcs_vfpcc <8 x i16> @xor_int16_257(<8 x i16> %a) {
; CHECKLE-LABEL: xor_int16_257:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i8 q1, #0x1
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int16_257:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i8 q1, #0x1
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <8 x i16> %a, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
ret <8 x i16> %b
}
define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() {
; CHECK-LABEL: mov_int16_258:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: mov.w r0, #258
; CHECK-NEXT: vdup.16 q0, r0
; CHECK-NEXT: bx lr
entry:
ret <8 x i16> <i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258>
}
define arm_aapcs_vfpcc <8 x i16> @xor_int16_258(<8 x i16> %a) {
; CHECKLE-LABEL: xor_int16_258:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: mov.w r0, #258
; CHECKLE-NEXT: vdup.16 q1, r0
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int16_258:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: mov.w r0, #258
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: vdup.16 q1, r0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <8 x i16> %a, <i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258>
ret <8 x i16> %b
}
define arm_aapcs_vfpcc <8 x i16> @mov_int16_32() {
; CHECKLE-LABEL: mov_int16_32:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: movw r0, #257
; CHECKLE-NEXT: movt r0, #256
; CHECKLE-NEXT: vdup.32 q0, r0
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: mov_int16_32:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: movw r0, #256
; CHECKBE-NEXT: movt r0, #257
; CHECKBE-NEXT: vdup.32 q0, r0
; CHECKBE-NEXT: bx lr
entry:
ret <8 x i16> <i16 257, i16 256, i16 257, i16 256, i16 257, i16 256, i16 257, i16 256>
}
define arm_aapcs_vfpcc <8 x i16> @xor_int16_32(<8 x i16> %a) {
; CHECKLE-LABEL: xor_int16_32:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: movw r0, #257
; CHECKLE-NEXT: movt r0, #256
; CHECKLE-NEXT: vdup.32 q1, r0
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int16_32:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: movw r0, #257
; CHECKBE-NEXT: vrev64.16 q1, q0
; CHECKBE-NEXT: movt r0, #256
; CHECKBE-NEXT: vdup.32 q0, r0
; CHECKBE-NEXT: veor q1, q1, q0
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <8 x i16> %a, <i16 257, i16 256, i16 257, i16 256, i16 257, i16 256, i16 257, i16 256>
ret <8 x i16> %b
}
define arm_aapcs_vfpcc <8 x i16> @mov_int16_64() {
; CHECK-LABEL: mov_int16_64:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i64 q0, #0xff0000000000ff
; CHECK-NEXT: bx lr
entry:
ret <8 x i16> <i16 255, i16 0, i16 0, i16 255, i16 255, i16 0, i16 0, i16 255>
}
define arm_aapcs_vfpcc <8 x i16> @xor_int16_64(<8 x i16> %a) {
; CHECKLE-LABEL: xor_int16_64:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q1, #0xff0000000000ff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int16_64:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff0000000000ff
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <8 x i16> %a, <i16 255, i16 0, i16 0, i16 255, i16 255, i16 0, i16 0, i16 255>
ret <8 x i16> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_1() {
; CHECK-LABEL: mov_int32_1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q0, #0x1
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_1(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i32 q1, #0x1
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i32 q1, #0x1
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_256() {
; CHECK-LABEL: mov_int32_256:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q0, #0x100
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 256, i32 256, i32 256, i32 256>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_256(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_256:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i32 q1, #0x100
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_256:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i32 q1, #0x100
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 256, i32 256, i32 256, i32 256>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_65536() {
; CHECK-LABEL: mov_int32_65536:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q0, #0x10000
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_65536(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_65536:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i32 q1, #0x10000
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_65536:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i32 q1, #0x10000
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 65536, i32 65536, i32 65536, i32 65536>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777216() {
; CHECK-LABEL: mov_int32_16777216:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q0, #0x1000000
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_16777216(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_16777216:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i32 q1, #0x1000000
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_16777216:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i32 q1, #0x1000000
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() {
; CHECK-LABEL: mov_int32_16777217:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r0, #1
; CHECK-NEXT: movt r0, #256
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 16777217, i32 16777217, i32 16777217, i32 16777217>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_16777217(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_16777217:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: movs r0, #1
; CHECKLE-NEXT: movt r0, #256
; CHECKLE-NEXT: vdup.32 q1, r0
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_16777217:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: movs r0, #1
; CHECKBE-NEXT: vrev64.32 q1, q0
; CHECKBE-NEXT: movt r0, #256
; CHECKBE-NEXT: vdup.32 q0, r0
; CHECKBE-NEXT: veor q1, q1, q0
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 16777217, i32 16777217, i32 16777217, i32 16777217>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_17919() {
; CHECK-LABEL: mov_int32_17919:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q0, #0x45ff
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 17919, i32 17919, i32 17919, i32 17919>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_17919(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_17919:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i32 q1, #0x45ff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_17919:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i32 q1, #0x45ff
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 17919, i32 17919, i32 17919, i32 17919>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_4587519() {
; CHECK-LABEL: mov_int32_4587519:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i32 q0, #0x45ffff
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 4587519, i32 4587519, i32 4587519, i32 4587519>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_4587519(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_4587519:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i32 q1, #0x45ffff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_4587519:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i32 q1, #0x45ffff
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 4587519, i32 4587519, i32 4587519, i32 4587519>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_m1() {
; CHECK-LABEL: mov_int32_m1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 q0, #0xff
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_m1(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_m1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmvn q0, q0
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_m1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i8 q1, #0xff
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_4294901760() {
; CHECK-LABEL: mov_int32_4294901760:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmvn.i32 q0, #0xffff
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_4294901760(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_4294901760:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmvn.i32 q1, #0xffff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_4294901760:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmvn.i32 q1, #0xffff
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() {
; CHECK-LABEL: mov_int32_4278190335:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r0, #255
; CHECK-NEXT: movt r0, #65280
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 4278190335, i32 4278190335, i32 4278190335, i32 4278190335>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_4278190335(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_4278190335:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: movs r0, #255
; CHECKLE-NEXT: movt r0, #65280
; CHECKLE-NEXT: vdup.32 q1, r0
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_4278190335:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: movs r0, #255
; CHECKBE-NEXT: vrev64.32 q1, q0
; CHECKBE-NEXT: movt r0, #65280
; CHECKBE-NEXT: vdup.32 q0, r0
; CHECKBE-NEXT: veor q1, q1, q0
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 4278190335, i32 4278190335, i32 4278190335, i32 4278190335>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278255615() {
; CHECK-LABEL: mov_int32_4278255615:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmvn.i32 q0, #0xff0000
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_4278255615(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_4278255615:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmvn.i32 q1, #0xff0000
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_4278255615:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmvn.i32 q1, #0xff0000
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_16908546() {
; CHECK-LABEL: mov_int32_16908546:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: mov.w r0, #258
; CHECK-NEXT: vdup.16 q0, r0
; CHECK-NEXT: bx lr
entry:
ret <4 x i32> <i32 16908546, i32 16908546, i32 16908546, i32 16908546>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_16908546(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_16908546:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: mov.w r0, #258
; CHECKLE-NEXT: vdup.16 q1, r0
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_16908546:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: mov.w r0, #258
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: vdup.16 q1, r0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 16908546, i32 16908546, i32 16908546, i32 16908546>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <4 x i32> @mov_int32_64() {
; CHECKLE-LABEL: mov_int32_64:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q0, #0xff00ffff00ff00
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: mov_int32_64:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q0, #0xff00ff0000ff00ff
; CHECKBE-NEXT: bx lr
entry:
ret <4 x i32> <i32 u0xff00ff00, i32 u0x00ff00ff, i32 u0xff00ff00, i32 u0x00ff00ff>
}
define arm_aapcs_vfpcc <4 x i32> @xor_int32_64(<4 x i32> %a) {
; CHECKLE-LABEL: xor_int32_64:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q1, #0xff00ffff00ff00
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int32_64:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff00ffff00ff00
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <4 x i32> %a, <i32 u0xff00ff00, i32 u0x00ff00ff, i32 u0xff00ff00, i32 u0x00ff00ff>
ret <4 x i32> %b
}
define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {
; CHECKLE-LABEL: mov_int64_1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: adr r0, .LCPI50_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
; CHECKLE-NEXT: .LCPI50_0:
; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324
; CHECKLE-NEXT: .long 0
; CHECKLE-NEXT: .long 1 @ double 4.9406564584124654E-324
; CHECKLE-NEXT: .long 0
;
; CHECKBE-LABEL: mov_int64_1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: adr r0, .LCPI50_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
; CHECKBE-NEXT: .LCPI50_0:
; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324
; CHECKBE-NEXT: .long 1
; CHECKBE-NEXT: .long 0 @ double 4.9406564584124654E-324
; CHECKBE-NEXT: .long 1
entry:
ret <2 x i64> <i64 1, i64 1>
}
define arm_aapcs_vfpcc <2 x i64> @xor_int64_1(<2 x i64> %a) {
; CHECKLE-LABEL: xor_int64_1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: adr r0, .LCPI51_0
; CHECKLE-NEXT: vldrw.u32 q1, [r0]
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
; CHECKLE-NEXT: .LCPI51_0:
; CHECKLE-NEXT: .long 1 @ 0x1
; CHECKLE-NEXT: .long 0 @ 0x0
; CHECKLE-NEXT: .long 1 @ 0x1
; CHECKLE-NEXT: .long 0 @ 0x0
;
; CHECKBE-LABEL: xor_int64_1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: adr r0, .LCPI51_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q2, q1
; CHECKBE-NEXT: veor q0, q0, q2
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
; CHECKBE-NEXT: .LCPI51_0:
; CHECKBE-NEXT: .long 0 @ 0x0
; CHECKBE-NEXT: .long 1 @ 0x1
; CHECKBE-NEXT: .long 0 @ 0x0
; CHECKBE-NEXT: .long 1 @ 0x1
entry:
%b = xor <2 x i64> %a, <i64 1, i64 1>
ret <2 x i64> %b
}
define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff() {
; CHECK-LABEL: mov_int64_ff:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i64 q0, #0xff
; CHECK-NEXT: bx lr
entry:
ret <2 x i64> <i64 255, i64 255>
}
define arm_aapcs_vfpcc <2 x i64> @xor_int64_ff(<2 x i64> %a) {
; CHECKLE-LABEL: xor_int64_ff:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q1, #0xff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int64_ff:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff00000000
; CHECKBE-NEXT: vrev64.32 q2, q1
; CHECKBE-NEXT: veor q0, q0, q2
; CHECKBE-NEXT: bx lr
entry:
%b = xor <2 x i64> %a, <i64 255, i64 255>
ret <2 x i64> %b
}
define arm_aapcs_vfpcc <2 x i64> @mov_int64_m1() {
; CHECK-LABEL: mov_int64_m1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i8 q0, #0xff
; CHECK-NEXT: bx lr
entry:
ret <2 x i64> <i64 -1, i64 -1>
}
define arm_aapcs_vfpcc <2 x i64> @xor_int64_m1(<2 x i64> %a) {
; CHECKLE-LABEL: xor_int64_m1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmvn q0, q0
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int64_m1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i8 q1, #0xff
; CHECKBE-NEXT: veor q0, q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <2 x i64> %a, <i64 -1, i64 -1>
ret <2 x i64> %b
}
define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff0000ff0000ffff() {
; CHECK-LABEL: mov_int64_ff0000ff0000ffff:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i64 q0, #0xff0000ff0000ffff
; CHECK-NEXT: bx lr
entry:
ret <2 x i64> <i64 18374687574888349695, i64 18374687574888349695>
}
define arm_aapcs_vfpcc <2 x i64> @xor_int64_ff0000ff0000ffff(<2 x i64> %a) {
; CHECKLE-LABEL: xor_int64_ff0000ff0000ffff:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q1, #0xff0000ff0000ffff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int64_ff0000ff0000ffff:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xffffff0000ff
; CHECKBE-NEXT: vrev64.32 q2, q1
; CHECKBE-NEXT: veor q0, q0, q2
; CHECKBE-NEXT: bx lr
entry:
%b = xor <2 x i64> %a, <i64 18374687574888349695, i64 18374687574888349695>
ret <2 x i64> %b
}
define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {
; CHECKLE-LABEL: mov_int64_f_0:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: adr r0, .LCPI58_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
; CHECKLE-NEXT: .LCPI58_0:
; CHECKLE-NEXT: .long 255 @ double 1.2598673968951787E-321
; CHECKLE-NEXT: .long 0
; CHECKLE-NEXT: .long 0 @ double 0
; CHECKLE-NEXT: .long 0
;
; CHECKBE-LABEL: mov_int64_f_0:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: adr r0, .LCPI58_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
; CHECKBE-NEXT: .LCPI58_0:
; CHECKBE-NEXT: .long 0 @ double 1.2598673968951787E-321
; CHECKBE-NEXT: .long 255
; CHECKBE-NEXT: .long 0 @ double 0
; CHECKBE-NEXT: .long 0
entry:
ret <2 x i64> <i64 255, i64 0>
}
define arm_aapcs_vfpcc <2 x i64> @xor_int64_f_0(<2 x i64> %a) {
; CHECKLE-LABEL: xor_int64_f_0:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: adr r0, .LCPI59_0
; CHECKLE-NEXT: vldrw.u32 q1, [r0]
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
; CHECKLE-NEXT: .LCPI59_0:
; CHECKLE-NEXT: .long 255 @ 0xff
; CHECKLE-NEXT: .long 0 @ 0x0
; CHECKLE-NEXT: .long 0 @ 0x0
; CHECKLE-NEXT: .long 0 @ 0x0
;
; CHECKBE-LABEL: xor_int64_f_0:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: adr r0, .LCPI59_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q2, q1
; CHECKBE-NEXT: veor q0, q0, q2
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
; CHECKBE-NEXT: .LCPI59_0:
; CHECKBE-NEXT: .long 0 @ 0x0
; CHECKBE-NEXT: .long 255 @ 0xff
; CHECKBE-NEXT: .long 0 @ 0x0
; CHECKBE-NEXT: .long 0 @ 0x0
entry:
%b = xor <2 x i64> %a, <i64 255, i64 0>
ret <2 x i64> %b
}
define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f000f0f() {
; CHECKLE-LABEL: mov_int64_0f000f0f:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q0, #0xff000000ff00ff
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: mov_int64_0f000f0f:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q0, #0xff00ff000000ff00
; CHECKBE-NEXT: bx lr
entry:
ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
}
define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f000f0f(<16 x i8> %a) {
; CHECKLE-LABEL: xor_int64_0f000f0f:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q1, #0xff000000ff00ff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int64_0f000f0f:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff000000ff00ff
; CHECKBE-NEXT: vrev64.8 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <16 x i8> %a, <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
ret <16 x i8> %b
}
define arm_aapcs_vfpcc <8 x i16> @mov_int64_ff00ffff() {
; CHECKLE-LABEL: mov_int64_ff00ffff:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q0, #0xffffffff0000ffff
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: mov_int64_ff00ffff:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q0, #0xffff0000ffffffff
; CHECKBE-NEXT: bx lr
entry:
ret <8 x i16> <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
}
define arm_aapcs_vfpcc <8 x i16> @xor_int64_ff00ffff(<8 x i16> %a) {
; CHECKLE-LABEL: xor_int64_ff00ffff:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q1, #0xffffffff0000ffff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int64_ff00ffff:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xffffffff0000ffff
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <8 x i16> %a, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
ret <8 x i16> %b
}
define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f0f0f0f0f0f0f0f() {
; CHECKLE-LABEL: mov_int64_0f0f0f0f0f0f0f0f:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i16 q0, #0xff
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: mov_int64_0f0f0f0f0f0f0f0f:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i16 q0, #0xff00
; CHECKBE-NEXT: bx lr
entry:
ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>
}
define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f0f0f0f0f0f0f0f(<16 x i8> %a) {
; CHECKLE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i16 q1, #0xff
; CHECKLE-NEXT: veor q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i16 q1, #0xff
; CHECKBE-NEXT: vrev64.8 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = xor <16 x i8> %a, <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>
ret <16 x i8> %b
}
define arm_aapcs_vfpcc <4 x float> @mov_float_1() {
; CHECK-LABEL: mov_float_1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: mov.w r0, #1065353216
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: bx lr
entry:
ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
}
define arm_aapcs_vfpcc <4 x float> @fadd_float_1(<4 x float> %a) {
; CHECKLE-MVE-LABEL: fadd_float_1:
; CHECKLE-MVE: @ %bb.0: @ %entry
; CHECKLE-MVE-NEXT: .save {r4, lr}
; CHECKLE-MVE-NEXT: push {r4, lr}
; CHECKLE-MVE-NEXT: .vsave {d8, d9}
; CHECKLE-MVE-NEXT: vpush {d8, d9}
; CHECKLE-MVE-NEXT: vmov q4, q0
; CHECKLE-MVE-NEXT: mov.w r1, #1065353216
; CHECKLE-MVE-NEXT: vmov r4, r0, d9
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: vmov s19, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: mov.w r1, #1065353216
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: vmov s18, r0
; CHECKLE-MVE-NEXT: mov.w r1, #1065353216
; CHECKLE-MVE-NEXT: vmov r4, r0, d8
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: vmov s17, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: mov.w r1, #1065353216
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: vmov s16, r0
; CHECKLE-MVE-NEXT: vmov q0, q4
; CHECKLE-MVE-NEXT: vpop {d8, d9}
; CHECKLE-MVE-NEXT: pop {r4, pc}
;
; CHECKLE-MVEFP-LABEL: fadd_float_1:
; CHECKLE-MVEFP: @ %bb.0: @ %entry
; CHECKLE-MVEFP-NEXT: vmov.f32 q1, #1.000000e+00
; CHECKLE-MVEFP-NEXT: vadd.f32 q0, q0, q1
; CHECKLE-MVEFP-NEXT: bx lr
;
; CHECKBE-LABEL: fadd_float_1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.f32 q1, #1.000000e+00
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: vadd.f32 q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = fadd <4 x float> %a, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
ret <4 x float> %b
}
define arm_aapcs_vfpcc <4 x float> @mov_float_m3() {
; CHECK-LABEL: mov_float_m3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: movt r0, #49216
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: bx lr
entry:
ret <4 x float> <float -3.000000e+00, float -3.000000e+00, float -3.000000e+00, float -3.000000e+00>
}
define arm_aapcs_vfpcc <4 x float> @fadd_float_m3(<4 x float> %a) {
; CHECKLE-MVE-LABEL: fadd_float_m3:
; CHECKLE-MVE: @ %bb.0: @ %entry
; CHECKLE-MVE-NEXT: .save {r4, r5, r7, lr}
; CHECKLE-MVE-NEXT: push {r4, r5, r7, lr}
; CHECKLE-MVE-NEXT: .vsave {d8, d9}
; CHECKLE-MVE-NEXT: vpush {d8, d9}
; CHECKLE-MVE-NEXT: vmov q4, q0
; CHECKLE-MVE-NEXT: movs r5, #0
; CHECKLE-MVE-NEXT: vmov r4, r0, d9
; CHECKLE-MVE-NEXT: movt r5, #49216
; CHECKLE-MVE-NEXT: mov r1, r5
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: vmov s19, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: mov r1, r5
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: vmov s18, r0
; CHECKLE-MVE-NEXT: mov r1, r5
; CHECKLE-MVE-NEXT: vmov r4, r0, d8
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: vmov s17, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: mov r1, r5
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: vmov s16, r0
; CHECKLE-MVE-NEXT: vmov q0, q4
; CHECKLE-MVE-NEXT: vpop {d8, d9}
; CHECKLE-MVE-NEXT: pop {r4, r5, r7, pc}
;
; CHECKLE-MVEFP-LABEL: fadd_float_m3:
; CHECKLE-MVEFP: @ %bb.0: @ %entry
; CHECKLE-MVEFP-NEXT: vmov.f32 q1, #-3.000000e+00
; CHECKLE-MVEFP-NEXT: vadd.f32 q0, q0, q1
; CHECKLE-MVEFP-NEXT: bx lr
;
; CHECKBE-LABEL: fadd_float_m3:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.f32 q1, #-3.000000e+00
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: vadd.f32 q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = fadd <4 x float> %a, <float -3.000000e+00, float -3.000000e+00, float -3.000000e+00, float -3.000000e+00>
ret <4 x float> %b
}
define arm_aapcs_vfpcc <8 x half> @mov_float16_1() {
; CHECK-LABEL: mov_float16_1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i16 q0, #0x3c00
; CHECK-NEXT: bx lr
entry:
ret <8 x half> <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00>
}
define arm_aapcs_vfpcc <8 x half> @fadd_float16_1(<8 x half> %a) {
; CHECKLE-MVE-LABEL: fadd_float16_1:
; CHECKLE-MVE: @ %bb.0: @ %entry
; CHECKLE-MVE-NEXT: .save {r4, lr}
; CHECKLE-MVE-NEXT: push {r4, lr}
; CHECKLE-MVE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECKLE-MVE-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECKLE-MVE-NEXT: vmov.u16 r0, q0[0]
; CHECKLE-MVE-NEXT: vmov q4, q0
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: vmov.i16 q6, #0x3c00
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[0]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[0], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[1]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[1]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[1], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[2]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[2]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[2], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[3]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[3]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[3], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[4]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[4]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[4], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[5]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[5]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[5], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[6]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[6]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[6], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[7]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[7]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[7], r0
; CHECKLE-MVE-NEXT: vmov q0, q5
; CHECKLE-MVE-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECKLE-MVE-NEXT: pop {r4, pc}
;
; CHECKLE-MVEFP-LABEL: fadd_float16_1:
; CHECKLE-MVEFP: @ %bb.0: @ %entry
; CHECKLE-MVEFP-NEXT: vmov.i16 q1, #0x3c00
; CHECKLE-MVEFP-NEXT: vadd.f16 q0, q0, q1
; CHECKLE-MVEFP-NEXT: bx lr
;
; CHECKBE-LABEL: fadd_float16_1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i16 q1, #0x3c00
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: vadd.f16 q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = fadd <8 x half> %a, <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00>
ret <8 x half> %b
}
define arm_aapcs_vfpcc <8 x half> @mov_float16_m3() {
; CHECK-LABEL: mov_float16_m3:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.i16 q0, #0xc200
; CHECK-NEXT: bx lr
entry:
ret <8 x half> <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00>
}
define arm_aapcs_vfpcc <8 x half> @fadd_float16_m3(<8 x half> %a) {
; CHECKLE-MVE-LABEL: fadd_float16_m3:
; CHECKLE-MVE: @ %bb.0: @ %entry
; CHECKLE-MVE-NEXT: .save {r4, lr}
; CHECKLE-MVE-NEXT: push {r4, lr}
; CHECKLE-MVE-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECKLE-MVE-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECKLE-MVE-NEXT: vmov.u16 r0, q0[0]
; CHECKLE-MVE-NEXT: vmov q4, q0
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: vmov.i16 q6, #0xc200
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[0]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[0], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[1]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[1]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[1], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[2]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[2]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[2], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[3]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[3]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[3], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[4]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[4]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[4], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[5]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[5]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[5], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[6]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[6]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[6], r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q4[7]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r4, r0
; CHECKLE-MVE-NEXT: vmov.u16 r0, q6[7]
; CHECKLE-MVE-NEXT: bl __aeabi_h2f
; CHECKLE-MVE-NEXT: mov r1, r0
; CHECKLE-MVE-NEXT: mov r0, r4
; CHECKLE-MVE-NEXT: bl __aeabi_fadd
; CHECKLE-MVE-NEXT: bl __aeabi_f2h
; CHECKLE-MVE-NEXT: vmov.16 q5[7], r0
; CHECKLE-MVE-NEXT: vmov q0, q5
; CHECKLE-MVE-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECKLE-MVE-NEXT: pop {r4, pc}
;
; CHECKLE-MVEFP-LABEL: fadd_float16_m3:
; CHECKLE-MVEFP: @ %bb.0: @ %entry
; CHECKLE-MVEFP-NEXT: vmov.i16 q1, #0xc200
; CHECKLE-MVEFP-NEXT: vadd.f16 q0, q0, q1
; CHECKLE-MVEFP-NEXT: bx lr
;
; CHECKBE-LABEL: fadd_float16_m3:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i16 q1, #0xc200
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: vadd.f16 q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%b = fadd <8 x half> %a, <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00>
ret <8 x half> %b
}
define arm_aapcs_vfpcc <2 x double> @mov_double_1() {
; CHECKLE-LABEL: mov_double_1:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: adr r0, .LCPI74_0
; CHECKLE-NEXT: vldrw.u32 q0, [r0]
; CHECKLE-NEXT: bx lr
; CHECKLE-NEXT: .p2align 4
; CHECKLE-NEXT: @ %bb.1:
; CHECKLE-NEXT: .LCPI74_0:
; CHECKLE-NEXT: .long 0 @ double 1
; CHECKLE-NEXT: .long 1072693248
; CHECKLE-NEXT: .long 0 @ double 1
; CHECKLE-NEXT: .long 1072693248
;
; CHECKBE-LABEL: mov_double_1:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: adr r0, .LCPI74_0
; CHECKBE-NEXT: vldrb.u8 q1, [r0]
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
; CHECKBE-NEXT: .p2align 4
; CHECKBE-NEXT: @ %bb.1:
; CHECKBE-NEXT: .LCPI74_0:
; CHECKBE-NEXT: .long 1072693248 @ double 1
; CHECKBE-NEXT: .long 0
; CHECKBE-NEXT: .long 1072693248 @ double 1
; CHECKBE-NEXT: .long 0
entry:
ret <2 x double> <double 1.000000e+00, double 1.000000e+00>
}
define arm_aapcs_vfpcc <16 x i8> @test(<16 x i8> %i) {
; CHECKLE-LABEL: test:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q1, #0xff000000ff00ff
; CHECKLE-NEXT: vorr q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: test:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff000000ff00ff
; CHECKBE-NEXT: vrev64.8 q2, q0
; CHECKBE-NEXT: vorr q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%o = or <16 x i8> %i, <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
ret <16 x i8> %o
}
define arm_aapcs_vfpcc <8 x i16> @test2(<8 x i16> %i) {
; CHECKLE-LABEL: test2:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: vmov.i64 q1, #0xffffffff0000ffff
; CHECKLE-NEXT: vorr q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: test2:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xffffffff0000ffff
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: vorr q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%o = or <8 x i16> %i, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
ret <8 x i16> %o
}
define arm_aapcs_vfpcc <4 x i32> @i1and_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECKLE-LABEL: i1and_vmov:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: cmp r0, #0
; CHECKLE-NEXT: mov.w r1, #15
; CHECKLE-NEXT: csetm r0, eq
; CHECKLE-NEXT: ands r0, r1
; CHECKLE-NEXT: vmsr p0, r0
; CHECKLE-NEXT: vpsel q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: i1and_vmov:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: cmp r0, #0
; CHECKBE-NEXT: mov.w r1, #15
; CHECKBE-NEXT: csetm r0, eq
; CHECKBE-NEXT: vrev64.32 q2, q1
; CHECKBE-NEXT: ands r0, r1
; CHECKBE-NEXT: vrev64.32 q1, q0
; CHECKBE-NEXT: vmsr p0, r0
; CHECKBE-NEXT: vpsel q1, q1, q2
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%c1 = icmp eq i32 %c, zeroinitializer
%broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 0
%broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer
%l699 = and <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false>
%s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %s
}
define arm_aapcs_vfpcc <4 x i32> @i1or_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) {
; CHECKLE-LABEL: i1or_vmov:
; CHECKLE: @ %bb.0: @ %entry
; CHECKLE-NEXT: cmp r0, #0
; CHECKLE-NEXT: mov.w r1, #15
; CHECKLE-NEXT: csetm r0, eq
; CHECKLE-NEXT: orrs r0, r1
; CHECKLE-NEXT: vmsr p0, r0
; CHECKLE-NEXT: vpsel q0, q0, q1
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: i1or_vmov:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: cmp r0, #0
; CHECKBE-NEXT: mov.w r1, #15
; CHECKBE-NEXT: csetm r0, eq
; CHECKBE-NEXT: vrev64.32 q2, q1
; CHECKBE-NEXT: orrs r0, r1
; CHECKBE-NEXT: vrev64.32 q1, q0
; CHECKBE-NEXT: vmsr p0, r0
; CHECKBE-NEXT: vpsel q1, q1, q2
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
%c1 = icmp eq i32 %c, zeroinitializer
%broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 0
%broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer
%l699 = or <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false>
%s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %s
}
define arm_aapcs_vfpcc <2 x i64> @v2i1and_vmov(<2 x i64> %a, <2 x i64> %b, i32 %c) {
; CHECK-LABEL: v2i1and_vmov:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #0, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq i32 %c, zeroinitializer
%broadcast.splatinsert1967 = insertelement <2 x i1> undef, i1 %c1, i32 0
%broadcast.splat1968 = shufflevector <2 x i1> %broadcast.splatinsert1967, <2 x i1> undef, <2 x i32> zeroinitializer
%l699 = and <2 x i1> %broadcast.splat1968, <i1 true, i1 false>
%s = select <2 x i1> %l699, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s
}
define arm_aapcs_vfpcc <2 x i64> @v2i1or_vmov(<2 x i64> %a, <2 x i64> %b, i32 %c) {
; CHECK-LABEL: v2i1or_vmov:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov.w r1, #255
; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: bfi r1, r0, #8, #8
; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%c1 = icmp eq i32 %c, zeroinitializer
%broadcast.splatinsert1967 = insertelement <2 x i1> undef, i1 %c1, i32 0
%broadcast.splat1968 = shufflevector <2 x i1> %broadcast.splatinsert1967, <2 x i1> undef, <2 x i32> zeroinitializer
%l699 = or <2 x i1> %broadcast.splat1968, <i1 true, i1 false>
%s = select <2 x i1> %l699, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s
}
define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
; CHECKLE-LABEL: and_v8i16_m1:
; CHECKLE: @ %bb.0:
; CHECKLE-NEXT: vbic.i32 q0, #0x10000
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: and_v8i16_m1:
; CHECKBE: @ %bb.0:
; CHECKBE-NEXT: vrev64.16 q1, q0
; CHECKBE-NEXT: vbic.i32 q1, #0x10000
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
%b = and <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
ret <8 x i16> %b
}
define arm_aapcs_vfpcc <8 x i16> @or_v8i16_1(<8 x i16> %a) {
; CHECKLE-LABEL: or_v8i16_1:
; CHECKLE: @ %bb.0:
; CHECKLE-NEXT: vorr.i32 q0, #0x10000
; CHECKLE-NEXT: bx lr
;
; CHECKBE-LABEL: or_v8i16_1:
; CHECKBE: @ %bb.0:
; CHECKBE-NEXT: vrev64.16 q1, q0
; CHECKBE-NEXT: vorr.i32 q1, #0x10000
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
%b = or <8 x i16> %a, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
ret <8 x i16> %b
}
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