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TheRock/compiler/amd-llvm/llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
derek.holloway 7502bf64a4
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LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s
; PR11494
define void @test(ptr nocapture %p) nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0:
; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpmaxsd (%rdi), %xmm0, %xmm0
; CHECK-NEXT: vmovdqu %xmm0, (%rdi)
; CHECK-NEXT: retq
%a = load <4 x i32>, ptr %p, align 1
%b = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> zeroinitializer) nounwind
%c = shufflevector <4 x i32> %b, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
%d = shufflevector <8 x i32> %c, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
store <4 x i32> %d, ptr %p, align 1
ret void
}
declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone