TheRock/compiler/amd-llvm/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx                -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl  -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL
--- |
  define void @test_insert_128_idx0() {
    ret void
  }

  define void @test_insert_128_idx0_undef() {
    ret void
  }

  define void @test_insert_128_idx1() {
    ret void
  }

  define void @test_insert_128_idx1_undef() {
    ret void
  }

...
---
name:            test_insert_128_idx0
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
#
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1

    ; AVX-LABEL: name: test_insert_128_idx0
    ; AVX: liveins: $ymm0, $ymm1
    ; AVX-NEXT: {{  $}}
    ; AVX-NEXT: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
    ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
    ; AVX-NEXT: [[VINSERTF128rri:%[0-9]+]]:vr256 = VINSERTF128rri [[COPY]], [[COPY1]], 0
    ; AVX-NEXT: $ymm0 = COPY [[VINSERTF128rri]]
    ; AVX-NEXT: RET 0, implicit $ymm0
    ;
    ; AVX512VL-LABEL: name: test_insert_128_idx0
    ; AVX512VL: liveins: $ymm0, $ymm1
    ; AVX512VL-NEXT: {{  $}}
    ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr256x = COPY $ymm0
    ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
    ; AVX512VL-NEXT: [[VINSERTF32X4Z256rri:%[0-9]+]]:vr256x = VINSERTF32X4Z256rri [[COPY]], [[COPY1]], 0
    ; AVX512VL-NEXT: $ymm0 = COPY [[VINSERTF32X4Z256rri]]
    ; AVX512VL-NEXT: RET 0, implicit $ymm0
    %0(<8 x s32>) = COPY $ymm0
    %1(<4 x s32>) = COPY $xmm1
    %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
    $ymm0 = COPY %2(<8 x s32>)
    RET 0, implicit $ymm0

...
---
name:            test_insert_128_idx0_undef
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
#
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1

    ; AVX-LABEL: name: test_insert_128_idx0_undef
    ; AVX: liveins: $ymm0, $ymm1
    ; AVX-NEXT: {{  $}}
    ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
    ; AVX-NEXT: [[DEF:%[0-9]+]]:vr256 = IMPLICIT_DEF
    ; AVX-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vr256 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_xmm
    ; AVX-NEXT: $ymm0 = COPY [[INSERT_SUBREG]]
    ; AVX-NEXT: RET 0, implicit $ymm0
    ;
    ; AVX512VL-LABEL: name: test_insert_128_idx0_undef
    ; AVX512VL: liveins: $ymm0, $ymm1
    ; AVX512VL-NEXT: {{  $}}
    ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1
    ; AVX512VL-NEXT: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
    ; AVX512VL-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vr256x = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_xmm
    ; AVX512VL-NEXT: $ymm0 = COPY [[INSERT_SUBREG]]
    ; AVX512VL-NEXT: RET 0, implicit $ymm0
    %0(<8 x s32>) = IMPLICIT_DEF
    %1(<4 x s32>) = COPY $xmm1
    %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
    $ymm0 = COPY %2(<8 x s32>)
    RET 0, implicit $ymm0

...
---
name:            test_insert_128_idx1
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
#
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1

    ; AVX-LABEL: name: test_insert_128_idx1
    ; AVX: liveins: $ymm0, $ymm1
    ; AVX-NEXT: {{  $}}
    ; AVX-NEXT: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
    ; AVX-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
    ; AVX-NEXT: [[VINSERTF128rri:%[0-9]+]]:vr256 = VINSERTF128rri [[COPY]], [[COPY1]], 1
    ; AVX-NEXT: $ymm0 = COPY [[VINSERTF128rri]]
    ; AVX-NEXT: RET 0, implicit $ymm0
    ;
    ; AVX512VL-LABEL: name: test_insert_128_idx1
    ; AVX512VL: liveins: $ymm0, $ymm1
    ; AVX512VL-NEXT: {{  $}}
    ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr256x = COPY $ymm0
    ; AVX512VL-NEXT: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
    ; AVX512VL-NEXT: [[VINSERTF32X4Z256rri:%[0-9]+]]:vr256x = VINSERTF32X4Z256rri [[COPY]], [[COPY1]], 1
    ; AVX512VL-NEXT: $ymm0 = COPY [[VINSERTF32X4Z256rri]]
    ; AVX512VL-NEXT: RET 0, implicit $ymm0
    %0(<8 x s32>) = COPY $ymm0
    %1(<4 x s32>) = COPY $xmm1
    %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
    $ymm0 = COPY %2(<8 x s32>)
    RET 0, implicit $ymm0
...
---
name:            test_insert_128_idx1_undef
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
#
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1

    ; AVX-LABEL: name: test_insert_128_idx1_undef
    ; AVX: liveins: $ymm0, $ymm1
    ; AVX-NEXT: {{  $}}
    ; AVX-NEXT: [[DEF:%[0-9]+]]:vr256 = IMPLICIT_DEF
    ; AVX-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm1
    ; AVX-NEXT: [[VINSERTF128rri:%[0-9]+]]:vr256 = VINSERTF128rri [[DEF]], [[COPY]], 1
    ; AVX-NEXT: $ymm0 = COPY [[VINSERTF128rri]]
    ; AVX-NEXT: RET 0, implicit $ymm0
    ;
    ; AVX512VL-LABEL: name: test_insert_128_idx1_undef
    ; AVX512VL: liveins: $ymm0, $ymm1
    ; AVX512VL-NEXT: {{  $}}
    ; AVX512VL-NEXT: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
    ; AVX512VL-NEXT: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1
    ; AVX512VL-NEXT: [[VINSERTF32X4Z256rri:%[0-9]+]]:vr256x = VINSERTF32X4Z256rri [[DEF]], [[COPY]], 1
    ; AVX512VL-NEXT: $ymm0 = COPY [[VINSERTF32X4Z256rri]]
    ; AVX512VL-NEXT: RET 0, implicit $ymm0
    %0(<8 x s32>) = IMPLICIT_DEF
    %1(<4 x s32>) = COPY $xmm1
    %2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
    $ymm0 = COPY %2(<8 x s32>)
    RET 0, implicit $ymm0
...