derek.holloway
7502bf64a4
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233 lines
9.8 KiB
LLVM
233 lines
9.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw -mattr=+avx512dq -mattr=+avx512vl| FileCheck %s
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define <8 x i1> @test(<2 x i1> %a) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $63, %xmm0, %xmm0
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; CHECK-NEXT: vpmovq2m %xmm0, %k0
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; CHECK-NEXT: kshiftlb $2, %k0, %k0
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; CHECK-NEXT: vpmovm2w %k0, %xmm0
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; CHECK-NEXT: retq
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%res = shufflevector <2 x i1> %a, <2 x i1> undef, <8 x i32> <i32 undef, i32 undef, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <8 x i1> %res
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}
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define <8 x i1> @test1(<2 x i1> %a) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $63, %xmm0, %xmm0
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; CHECK-NEXT: vpmovq2m %xmm0, %k0
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; CHECK-NEXT: kshiftlb $4, %k0, %k0
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; CHECK-NEXT: vpmovm2w %k0, %xmm0
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; CHECK-NEXT: retq
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%res = shufflevector <2 x i1> %a, <2 x i1> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 undef, i32 undef>
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ret <8 x i1> %res
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}
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define <8 x i1> @test2(<2 x i1> %a) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $63, %xmm0, %xmm0
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; CHECK-NEXT: vpmovq2m %xmm0, %k0
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; CHECK-NEXT: kshiftlb $4, %k0, %k0
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; CHECK-NEXT: vpmovm2w %k0, %xmm0
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; CHECK-NEXT: retq
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%res = shufflevector <2 x i1> %a, <2 x i1> zeroinitializer, <8 x i32> <i32 3, i32 3, i32 undef, i32 undef, i32 0, i32 1, i32 undef, i32 undef>
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ret <8 x i1> %res
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}
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define <8 x i1> @test3(<4 x i1> %a) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
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; CHECK-NEXT: vpmovd2m %xmm0, %k0
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; CHECK-NEXT: vpmovm2w %k0, %xmm0
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; CHECK-NEXT: retq
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%res = shufflevector <4 x i1> %a, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i1> %res
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}
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define <8 x i1> @test4(<4 x i1> %a, <4 x i1>%b) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; CHECK-NEXT: vpslld $31, %ymm0, %ymm0
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; CHECK-NEXT: vpmovd2m %ymm0, %k0
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; CHECK-NEXT: vpmovm2w %k0, %xmm0
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%res = shufflevector <4 x i1> %a, <4 x i1> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i1> %res
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}
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define <4 x i1> @test5(<2 x i1> %a, <2 x i1>%b) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; CHECK-NEXT: vpsllq $63, %ymm0, %ymm0
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; CHECK-NEXT: vpmovq2m %ymm0, %k0
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; CHECK-NEXT: vpmovm2d %k0, %xmm0
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%res = shufflevector <2 x i1> %a, <2 x i1> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i1> %res
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}
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define <16 x i1> @test6(<2 x i1> %a, <2 x i1>%b) {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $63, %xmm1, %xmm1
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; CHECK-NEXT: vpmovq2m %xmm1, %k0
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; CHECK-NEXT: vpsllq $63, %xmm0, %xmm0
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; CHECK-NEXT: vpmovq2m %xmm0, %k1
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; CHECK-NEXT: kshiftlb $2, %k0, %k0
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; CHECK-NEXT: korw %k0, %k1, %k0
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; CHECK-NEXT: vpmovm2b %k0, %xmm0
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; CHECK-NEXT: retq
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%res = shufflevector <2 x i1> %a, <2 x i1> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <16 x i1> %res
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}
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define <32 x i1> @test7(<4 x i1> %a, <4 x i1>%b) {
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; CHECK-LABEL: test7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; CHECK-NEXT: vpslld $31, %ymm0, %ymm0
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; CHECK-NEXT: vpmovd2m %ymm0, %k0
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; CHECK-NEXT: vpmovm2b %k0, %ymm0
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; CHECK-NEXT: retq
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%res = shufflevector <4 x i1> %a, <4 x i1> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <32 x i1> %res
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}
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define <64 x i1> @test8(<8 x i1> %a, <8 x i1>%b) {
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; CHECK-LABEL: test8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllw $15, %xmm1, %xmm1
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; CHECK-NEXT: vpmovw2m %xmm1, %k0
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; CHECK-NEXT: vpsllw $15, %xmm0, %xmm0
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; CHECK-NEXT: vpmovw2m %xmm0, %k1
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; CHECK-NEXT: kunpckdq %k1, %k0, %k0
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; CHECK-NEXT: vpmovm2b %k0, %zmm0
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; CHECK-NEXT: retq
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%res = shufflevector <8 x i1> %a, <8 x i1> %b, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <64 x i1> %res
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}
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define <4 x i1> @test9(<8 x i1> %a, <8 x i1> %b) {
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; CHECK-LABEL: test9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllw $15, %xmm0, %xmm0
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; CHECK-NEXT: vpmovw2m %xmm0, %k0
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; CHECK-NEXT: kshiftrb $4, %k0, %k0
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; CHECK-NEXT: vpmovm2d %k0, %xmm0
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; CHECK-NEXT: retq
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%res = shufflevector <8 x i1> %a, <8 x i1> %b, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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ret <4 x i1> %res
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}
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define <2 x i1> @test10(<4 x i1> %a, <4 x i1> %b) {
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; CHECK-LABEL: test10:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
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; CHECK-NEXT: vpmovd2m %xmm0, %k0
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; CHECK-NEXT: kshiftrb $2, %k0, %k0
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; CHECK-NEXT: vpmovm2q %k0, %xmm0
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; CHECK-NEXT: retq
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%res = shufflevector <4 x i1> %a, <4 x i1> %b, <2 x i32> <i32 2, i32 3>
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ret <2 x i1> %res
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}
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define <8 x i1> @test11(<4 x i1> %a, <4 x i1>%b) {
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; CHECK-LABEL: test11:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpslld $31, %xmm0, %xmm0
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; CHECK-NEXT: vpmovd2m %xmm0, %k0
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; CHECK-NEXT: kshiftlb $4, %k0, %k0
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; CHECK-NEXT: vpmovm2w %k0, %xmm0
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; CHECK-NEXT: retq
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%res = shufflevector <4 x i1> %a, <4 x i1> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
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ret <8 x i1> %res
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}
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define <16 x i1> @test12(<2 x i1> %a) {
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; CHECK-LABEL: test12:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $63, %xmm0, %xmm0
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; CHECK-NEXT: vpmovq2m %xmm0, %k0
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; CHECK-NEXT: kshiftlw $10, %k0, %k0
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; CHECK-NEXT: vpmovm2b %k0, %xmm0
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; CHECK-NEXT: retq
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%res = shufflevector <2 x i1> %a, <2 x i1> zeroinitializer, <16 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <16 x i1> %res
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}
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define <32 x i1> @test13(<2 x i1> %a) {
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; CHECK-LABEL: test13:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $63, %xmm0, %xmm0
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; CHECK-NEXT: vpmovq2m %xmm0, %k0
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; CHECK-NEXT: kshiftld $10, %k0, %k0
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; CHECK-NEXT: vpmovm2b %k0, %ymm0
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; CHECK-NEXT: retq
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%res = shufflevector <2 x i1> %a, <2 x i1> zeroinitializer, <32 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <32 x i1> %res
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}
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define <64 x i1> @test14(<2 x i1> %a) {
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; CHECK-LABEL: test14:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpsllq $63, %xmm0, %xmm0
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; CHECK-NEXT: vpmovq2m %xmm0, %k0
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; CHECK-NEXT: kshiftlq $10, %k0, %k0
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; CHECK-NEXT: vpmovm2b %k0, %zmm0
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; CHECK-NEXT: retq
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%res = shufflevector <2 x i1> %a, <2 x i1> zeroinitializer, <64 x i32> <i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <64 x i1> %res
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}
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; Make sure we can recognize this shuffle as an insertion in to a zero vector.
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define i8 @test15(<2 x i64> %x) {
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; CHECK-LABEL: test15:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vptestnmq %xmm0, %xmm0, %k0
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; CHECK-NEXT: kmovd %k0, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%a = icmp eq <2 x i64> %x, zeroinitializer
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%b = shufflevector <2 x i1> %a, <2 x i1> <i1 false, i1 undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%c = bitcast <8 x i1> %b to i8
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ret i8 %c
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}
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; Ensure multiple uses of mask source doesn't cause infinite loop
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define <16 x i8> @test_insert_subvector_v8i1_v16i1(i8 %a0) {
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; CHECK-LABEL: test_insert_subvector_v8i1_v16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorb $1, %dil
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; CHECK-NEXT: kmovd %edi, %k1
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; CHECK-NEXT: kmovb %k1, %k2
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; CHECK-NEXT: vmovdqu8 0, %xmm0 {%k2} {z}
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; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; CHECK-NEXT: vmovdqu64 %zmm1, 0 {%k1}
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%xor = xor i8 %a0, 1
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%zext = zext i8 %xor to i16
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%mask16 = bitcast i16 %zext to <16 x i1>
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%load = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr null, <16 x i1> %mask16, <16 x i8> zeroinitializer)
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%mask8 = bitcast i8 %xor to <8 x i1>
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call void @llvm.masked.store.v8i64.p0(<8 x i64> zeroinitializer, ptr null, <8 x i1> %mask8)
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ret <16 x i8> %load
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}
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