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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE2
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE2
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2
;------------------------------ 32-bit shuffles -------------------------------;
define <4 x i32> @shuffle_i32_of_shl_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; SSE2-LABEL: shuffle_i32_of_shl_i16:
; SSE2: # %bb.0:
; SSE2-NEXT: psllw $15, %xmm0
; SSE2-NEXT: psllw $15, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i32_of_shl_i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsllw $15, %xmm0, %xmm0
; AVX2-NEXT: vpsllw $15, %xmm1, %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %x, i32 15)
%i2 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %y, i32 15)
%i3 = bitcast <8 x i16> %i1 to <4 x i32>
%i4 = bitcast <8 x i16> %i2 to <4 x i32>
%i5 = shufflevector <4 x i32> %i3, <4 x i32> %i4, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
ret <4 x i32> %i5
}
define <4 x i32> @shuffle_i32_of_lshr_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; SSE2-LABEL: shuffle_i32_of_lshr_i16:
; SSE2: # %bb.0:
; SSE2-NEXT: psrlw $15, %xmm0
; SSE2-NEXT: psrlw $15, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i32_of_lshr_i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $15, %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $15, %xmm1, %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %x, i32 15)
%i2 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %y, i32 15)
%i3 = bitcast <8 x i16> %i1 to <4 x i32>
%i4 = bitcast <8 x i16> %i2 to <4 x i32>
%i5 = shufflevector <4 x i32> %i3, <4 x i32> %i4, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
ret <4 x i32> %i5
}
define <4 x i32> @shuffle_i32_of_ashr_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; SSE2-LABEL: shuffle_i32_of_ashr_i16:
; SSE2: # %bb.0:
; SSE2-NEXT: psraw $15, %xmm0
; SSE2-NEXT: psraw $15, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i32_of_ashr_i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsraw $15, %xmm0, %xmm0
; AVX2-NEXT: vpsraw $15, %xmm1, %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %x, i32 15)
%i2 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %y, i32 15)
%i3 = bitcast <8 x i16> %i1 to <4 x i32>
%i4 = bitcast <8 x i16> %i2 to <4 x i32>
%i5 = shufflevector <4 x i32> %i3, <4 x i32> %i4, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
ret <4 x i32> %i5
}
define <4 x i32> @shuffle_i32_of_shl_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE2-LABEL: shuffle_i32_of_shl_i32:
; SSE2: # %bb.0:
; SSE2-NEXT: pslld $31, %xmm0
; SSE2-NEXT: pslld $31, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i32_of_shl_i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %x, i32 31)
%i2 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %y, i32 31)
%i3 = shufflevector <4 x i32> %i1, <4 x i32> %i2, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
ret <4 x i32> %i3
}
define <4 x i32> @shuffle_i32_of_lshr_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE2-LABEL: shuffle_i32_of_lshr_i32:
; SSE2: # %bb.0:
; SSE2-NEXT: psrld $31, %xmm0
; SSE2-NEXT: psrld $31, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i32_of_lshr_i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; AVX2-NEXT: vpsrld $31, %xmm1, %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %x, i32 31)
%i2 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %y, i32 31)
%i3 = shufflevector <4 x i32> %i1, <4 x i32> %i2, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
ret <4 x i32> %i3
}
define <4 x i32> @shuffle_i32_of_ashr_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE2-LABEL: shuffle_i32_of_ashr_i32:
; SSE2: # %bb.0:
; SSE2-NEXT: psrad $31, %xmm0
; SSE2-NEXT: psrad $31, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i32_of_ashr_i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrad $31, %xmm0, %xmm0
; AVX2-NEXT: vpsrad $31, %xmm1, %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %x, i32 31)
%i2 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %y, i32 31)
%i3 = shufflevector <4 x i32> %i1, <4 x i32> %i2, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
ret <4 x i32> %i3
}
define <4 x i32> @shuffle_i32_of_shl_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSE2-LABEL: shuffle_i32_of_shl_i64:
; SSE2: # %bb.0:
; SSE2-NEXT: psllq $63, %xmm0
; SSE2-NEXT: psllq $63, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i32_of_shl_i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsllq $63, %xmm0, %xmm0
; AVX2-NEXT: vpsllq $63, %xmm1, %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %x, i32 63)
%i2 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %y, i32 63)
%i3 = bitcast <2 x i64> %i1 to <4 x i32>
%i4 = bitcast <2 x i64> %i2 to <4 x i32>
%i5 = shufflevector <4 x i32> %i3, <4 x i32> %i4, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
ret <4 x i32> %i5
}
define <4 x i32> @shuffle_i32_of_lshr_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSE2-LABEL: shuffle_i32_of_lshr_i64:
; SSE2: # %bb.0:
; SSE2-NEXT: psrlq $63, %xmm0
; SSE2-NEXT: psrlq $63, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm0[1,0]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i32_of_lshr_i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlq $63, %xmm0, %xmm0
; AVX2-NEXT: vpsrlq $63, %xmm1, %xmm1
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm1[3,2],xmm0[1,0]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %x, i32 63)
%i2 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %y, i32 63)
%i3 = bitcast <2 x i64> %i1 to <4 x i32>
%i4 = bitcast <2 x i64> %i2 to <4 x i32>
%i5 = shufflevector <4 x i32> %i3, <4 x i32> %i4, <4 x i32> <i32 7, i32 6, i32 1, i32 0>
ret <4 x i32> %i5
}
;------------------------------ 64-bit shuffles -------------------------------;
define <2 x i64> @shuffle_i64_of_shl_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; SSE2-LABEL: shuffle_i64_of_shl_i16:
; SSE2: # %bb.0:
; SSE2-NEXT: psllw $15, %xmm0
; SSE2-NEXT: psllw $15, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i64_of_shl_i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsllw $15, %xmm0, %xmm0
; AVX2-NEXT: vpsllw $15, %xmm1, %xmm1
; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %x, i32 15)
%i2 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %y, i32 15)
%i3 = bitcast <8 x i16> %i1 to <2 x i64>
%i4 = bitcast <8 x i16> %i2 to <2 x i64>
%i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %i5
}
define <2 x i64> @shuffle_i64_of_lshr_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; SSE2-LABEL: shuffle_i64_of_lshr_i16:
; SSE2: # %bb.0:
; SSE2-NEXT: psrlw $15, %xmm0
; SSE2-NEXT: psrlw $15, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i64_of_lshr_i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlw $15, %xmm0, %xmm0
; AVX2-NEXT: vpsrlw $15, %xmm1, %xmm1
; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %x, i32 15)
%i2 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %y, i32 15)
%i3 = bitcast <8 x i16> %i1 to <2 x i64>
%i4 = bitcast <8 x i16> %i2 to <2 x i64>
%i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %i5
}
define <2 x i64> @shuffle_i64_of_ashr_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; SSE2-LABEL: shuffle_i64_of_ashr_i16:
; SSE2: # %bb.0:
; SSE2-NEXT: psraw $15, %xmm0
; SSE2-NEXT: psraw $15, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i64_of_ashr_i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsraw $15, %xmm0, %xmm0
; AVX2-NEXT: vpsraw $15, %xmm1, %xmm1
; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %x, i32 15)
%i2 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %y, i32 15)
%i3 = bitcast <8 x i16> %i1 to <2 x i64>
%i4 = bitcast <8 x i16> %i2 to <2 x i64>
%i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %i5
}
define <2 x i64> @shuffle_i64_of_shl_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE2-LABEL: shuffle_i64_of_shl_i32:
; SSE2: # %bb.0:
; SSE2-NEXT: pslld $31, %xmm0
; SSE2-NEXT: pslld $31, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i64_of_shl_i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1
; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %x, i32 31)
%i2 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %y, i32 31)
%i3 = bitcast <4 x i32> %i1 to <2 x i64>
%i4 = bitcast <4 x i32> %i2 to <2 x i64>
%i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %i5
}
define <2 x i64> @shuffle_i64_of_lshr_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE2-LABEL: shuffle_i64_of_lshr_i32:
; SSE2: # %bb.0:
; SSE2-NEXT: psrld $31, %xmm0
; SSE2-NEXT: psrld $31, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i64_of_lshr_i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
; AVX2-NEXT: vpsrld $31, %xmm1, %xmm1
; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %x, i32 31)
%i2 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %y, i32 31)
%i3 = bitcast <4 x i32> %i1 to <2 x i64>
%i4 = bitcast <4 x i32> %i2 to <2 x i64>
%i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %i5
}
define <2 x i64> @shuffle_i64_of_ashr_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; SSE2-LABEL: shuffle_i64_of_ashr_i32:
; SSE2: # %bb.0:
; SSE2-NEXT: psrad $31, %xmm0
; SSE2-NEXT: psrad $31, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i64_of_ashr_i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrad $31, %xmm0, %xmm0
; AVX2-NEXT: vpsrad $31, %xmm1, %xmm1
; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %x, i32 31)
%i2 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %y, i32 31)
%i3 = bitcast <4 x i32> %i1 to <2 x i64>
%i4 = bitcast <4 x i32> %i2 to <2 x i64>
%i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %i5
}
define <2 x i64> @shuffle_i64_of_shl_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSE2-LABEL: shuffle_i64_of_shl_i64:
; SSE2: # %bb.0:
; SSE2-NEXT: psllq $63, %xmm0
; SSE2-NEXT: psllq $63, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i64_of_shl_i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsllq $63, %xmm0, %xmm0
; AVX2-NEXT: vpsllq $63, %xmm1, %xmm1
; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %x, i32 63)
%i2 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %y, i32 63)
%i3 = bitcast <2 x i64> %i1 to <2 x i64>
%i4 = bitcast <2 x i64> %i2 to <2 x i64>
%i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %i5
}
define <2 x i64> @shuffle_i64_of_lshr_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; SSE2-LABEL: shuffle_i64_of_lshr_i64:
; SSE2: # %bb.0:
; SSE2-NEXT: psrlq $63, %xmm0
; SSE2-NEXT: psrlq $63, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,3],xmm0[0,1]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: ret{{[l|q]}}
;
; AVX2-LABEL: shuffle_i64_of_lshr_i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vpsrlq $63, %xmm0, %xmm0
; AVX2-NEXT: vpsrlq $63, %xmm1, %xmm1
; AVX2-NEXT: vpalignr {{.*#+}} xmm0 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT: ret{{[l|q]}}
%i1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %x, i32 63)
%i2 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %y, i32 63)
%i3 = bitcast <2 x i64> %i1 to <2 x i64>
%i4 = bitcast <2 x i64> %i2 to <2 x i64>
%i5 = shufflevector <2 x i64> %i3, <2 x i64> %i4, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %i5
}
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