derek.holloway
7502bf64a4
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48 lines
2.2 KiB
LLVM
48 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge | FileCheck %s --check-prefixes=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX
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define <4 x double> @concat_fmin_v4f64_v2f64(<2 x double> %a0, <2 x double> %a1) {
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; SSE-LABEL: concat_fmin_v4f64_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: xorpd %xmm2, %xmm2
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; SSE-NEXT: minpd %xmm2, %xmm0
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; SSE-NEXT: minpd %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: concat_fmin_v4f64_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%v0 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> zeroinitializer)
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%v1 = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a1, <2 x double> zeroinitializer)
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%res = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x double> %res
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}
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define <8 x float> @concat_fmin_v8f32_v4f32(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: concat_fmin_v8f32_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm2, %xmm2
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; SSE-NEXT: minps %xmm2, %xmm0
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; SSE-NEXT: minps %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: concat_fmin_v8f32_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vminps %ymm1, %ymm0, %ymm0
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; AVX-NEXT: retq
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%v0 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> zeroinitializer)
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%v1 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a1, <4 x float> zeroinitializer)
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%res = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x float> %res
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}
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