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TheRock/compiler/amd-llvm/llvm/test/CodeGen/X86/combine-pclmul.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s
define <2 x i64> @test_extract_pclmulqdq_v4i64_v2i64(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-LABEL: test_extract_pclmulqdq_v4i64_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $1, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
%clmul = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a0, <4 x i64> %a1, i8 1)
%res = shufflevector <4 x i64> %clmul, <4 x i64> poison, <2 x i32> <i32 0, i32 1>
ret <2 x i64> %res
}
define <4 x i64> @test_extract_pclmulqdq_v8i64_v4i64(<8 x i64> %a0, <8 x i64> %a1) {
; CHECK-LABEL: test_extract_pclmulqdq_v8i64_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $1, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
%clmul = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %a0, <8 x i64> %a1, i8 1)
%res = shufflevector <8 x i64> %clmul, <8 x i64> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i64> %res
}
define <4 x i64> @test_concat_pclmulqdq_v4i64_v2i64(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-LABEL: test_concat_pclmulqdq_v4i64_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $0, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
%lo0 = shufflevector <4 x i64> %a0, <4 x i64> poison, <2 x i32> <i32 0, i32 1>
%lo1 = shufflevector <4 x i64> %a1, <4 x i64> poison, <2 x i32> <i32 0, i32 1>
%hi0 = shufflevector <4 x i64> %a0, <4 x i64> poison, <2 x i32> <i32 2, i32 3>
%hi1 = shufflevector <4 x i64> %a1, <4 x i64> poison, <2 x i32> <i32 2, i32 3>
%lo = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %lo0, <2 x i64> %lo1, i8 0)
%hi = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %hi0, <2 x i64> %hi1, i8 0)
%res = shufflevector <2 x i64> %lo, <2 x i64> %hi, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i64> %res
}
define <8 x i64> @test_concat_pclmulqdq_v8i64_v2i64(<8 x i64> %a0, <8 x i64> %a1) {
; CHECK-LABEL: test_concat_pclmulqdq_v8i64_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $1, %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
%x0 = shufflevector <8 x i64> %a0, <8 x i64> poison, <2 x i32> <i32 0, i32 1>
%x1 = shufflevector <8 x i64> %a1, <8 x i64> poison, <2 x i32> <i32 0, i32 1>
%y0 = shufflevector <8 x i64> %a0, <8 x i64> poison, <2 x i32> <i32 2, i32 3>
%y1 = shufflevector <8 x i64> %a1, <8 x i64> poison, <2 x i32> <i32 2, i32 3>
%z0 = shufflevector <8 x i64> %a0, <8 x i64> poison, <2 x i32> <i32 4, i32 5>
%z1 = shufflevector <8 x i64> %a1, <8 x i64> poison, <2 x i32> <i32 4, i32 5>
%w0 = shufflevector <8 x i64> %a0, <8 x i64> poison, <2 x i32> <i32 6, i32 7>
%w1 = shufflevector <8 x i64> %a1, <8 x i64> poison, <2 x i32> <i32 6, i32 7>
%x = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %x0, <2 x i64> %x1, i8 1)
%y = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %y0, <2 x i64> %y1, i8 1)
%z = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %z0, <2 x i64> %z1, i8 1)
%w = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %w0, <2 x i64> %w1, i8 1)
%lo = shufflevector <2 x i64> %x, <2 x i64> %y, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%hi = shufflevector <2 x i64> %z, <2 x i64> %w, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%res = shufflevector <4 x i64> %lo, <4 x i64> %hi, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i64> %res
}
define <8 x i64> @test_concat_pclmulqdq_v8i64_v4i64(<8 x i64> %a0, <8 x i64> %a1) {
; CHECK-LABEL: test_concat_pclmulqdq_v8i64_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $17, %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
%lo0 = shufflevector <8 x i64> %a0, <8 x i64> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%lo1 = shufflevector <8 x i64> %a1, <8 x i64> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%hi0 = shufflevector <8 x i64> %a0, <8 x i64> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%hi1 = shufflevector <8 x i64> %a1, <8 x i64> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%lo = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %lo0, <4 x i64> %lo1, i8 17)
%hi = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %hi0, <4 x i64> %hi1, i8 17)
%res = shufflevector <4 x i64> %lo, <4 x i64> %hi, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i64> %res
}
define <2 x i64> @test_shuffle_pclmulqdq_v2i64(<2 x i64> %a0, <2 x i64> %a1) {
; CHECK-LABEL: test_shuffle_pclmulqdq_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $16, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%s0 = shufflevector <2 x i64> %a0, <2 x i64> poison, <2 x i32> <i32 1, i32 0>
%s1 = shufflevector <2 x i64> %a1, <2 x i64> poison, <2 x i32> <i32 1, i32 0>
%clmul = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %s0, <2 x i64> %s1, i8 1)
ret <2 x i64> %clmul
}
define <4 x i64> @test_shuffle_pclmulqdq_v4i64(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-LABEL: test_shuffle_pclmulqdq_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $1, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
%s0 = shufflevector <4 x i64> %a0, <4 x i64> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
%s1 = shufflevector <4 x i64> %a1, <4 x i64> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
%clmul = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %s0, <4 x i64> %s1, i8 16)
ret <4 x i64> %clmul
}
define <8 x i64> @test_shuffle_pclmulqdq_v8i64(<8 x i64> %a0, <8 x i64> %a1) {
; CHECK-LABEL: test_shuffle_pclmulqdq_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $0, %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
%s0 = shufflevector <8 x i64> %a0, <8 x i64> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
%s1 = shufflevector <8 x i64> %a1, <8 x i64> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
%clmul = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %s0, <8 x i64> %s1, i8 17)
ret <8 x i64> %clmul
}
define <2 x i64> @test_demanded_elts_pclmulqdq_0(<2 x i64> %a0, <2 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%1 = insertelement <2 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <2 x i64> %a1, i64 %s1, i64 1
%3 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %2, i8 0)
ret <2 x i64> %3
}
define <2 x i64> @test_demanded_elts_pclmulqdq_1(<2 x i64> %a0, <2 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0
; CHECK-NEXT: vpclmulqdq $1, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%1 = insertelement <2 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <2 x i64> %a1, i64 %s1, i64 1
%3 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %2, i8 1)
ret <2 x i64> %3
}
define <2 x i64> @test_demanded_elts_pclmulqdq_16(<2 x i64> %a0, <2 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_16:
; CHECK: # %bb.0:
; CHECK-NEXT: vpinsrq $1, %rsi, %xmm0, %xmm1
; CHECK-NEXT: vpclmulqdq $16, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%1 = insertelement <2 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <2 x i64> %a1, i64 %s1, i64 1
%3 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %2, i8 16)
ret <2 x i64> %3
}
define <2 x i64> @test_demanded_elts_pclmulqdq_17(<2 x i64> %a0, <2 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_17:
; CHECK: # %bb.0:
; CHECK-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0
; CHECK-NEXT: vpinsrq $1, %rsi, %xmm0, %xmm1
; CHECK-NEXT: vpclmulqdq $17, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%1 = insertelement <2 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <2 x i64> %a1, i64 %s1, i64 1
%3 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %2, i8 17)
ret <2 x i64> %3
}
define <4 x i64> @test_demanded_elts_pclmulqdq_256_0(<4 x i64> %a0, <4 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_256_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $0, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = insertelement <4 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <4 x i64> %a1, i64 %s1, i64 1
%3 = insertelement <4 x i64> %1, i64 %s0, i64 3
%4 = insertelement <4 x i64> %2, i64 %s1, i64 3
%res = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %3, <4 x i64> %4, i8 0)
ret <4 x i64> %res
}
define <4 x i64> @test_demanded_elts_pclmulqdq_256_1(<4 x i64> %a0, <4 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_256_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0
; CHECK-NEXT: vpbroadcastq %rdi, %ymm2
; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm2[6,7]
; CHECK-NEXT: vpclmulqdq $1, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = insertelement <4 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <4 x i64> %a1, i64 %s1, i64 1
%3 = insertelement <4 x i64> %1, i64 %s0, i64 3
%4 = insertelement <4 x i64> %2, i64 %s1, i64 3
%res = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %3, <4 x i64> %4, i8 1)
ret <4 x i64> %res
}
define <4 x i64> @test_demanded_elts_pclmulqdq_256_16(<4 x i64> %a0, <4 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_256_16:
; CHECK: # %bb.0:
; CHECK-NEXT: vpinsrq $1, %rsi, %xmm0, %xmm1
; CHECK-NEXT: vpbroadcastq %rsi, %ymm2
; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm2[6,7]
; CHECK-NEXT: vpclmulqdq $16, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = insertelement <4 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <4 x i64> %a1, i64 %s1, i64 1
%3 = insertelement <4 x i64> %1, i64 %s0, i64 3
%4 = insertelement <4 x i64> %2, i64 %s1, i64 3
%res = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %3, <4 x i64> %4, i8 16)
ret <4 x i64> %res
}
define <4 x i64> @test_demanded_elts_pclmulqdq_256_17(<4 x i64> %a0, <4 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_256_17:
; CHECK: # %bb.0:
; CHECK-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0
; CHECK-NEXT: vpinsrq $1, %rsi, %xmm0, %xmm1
; CHECK-NEXT: vpbroadcastq %rdi, %ymm2
; CHECK-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm2[6,7]
; CHECK-NEXT: vpbroadcastq %rsi, %ymm2
; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm2[6,7]
; CHECK-NEXT: vpclmulqdq $17, %ymm1, %ymm0, %ymm0
; CHECK-NEXT: retq
%1 = insertelement <4 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <4 x i64> %a1, i64 %s1, i64 1
%3 = insertelement <4 x i64> %1, i64 %s0, i64 3
%4 = insertelement <4 x i64> %2, i64 %s1, i64 3
%res = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %3, <4 x i64> %4, i8 17)
ret <4 x i64> %res
}
define <8 x i64> @test_demanded_elts_pclmulqdq_512_0(<8 x i64> %a0, <8 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_512_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $0, %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
%1 = insertelement <8 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <8 x i64> %a1, i64 %s1, i64 1
%3 = insertelement <8 x i64> %1, i64 %s0, i64 3
%4 = insertelement <8 x i64> %2, i64 %s1, i64 3
%5 = insertelement <8 x i64> %3, i64 %s0, i64 5
%6 = insertelement <8 x i64> %4, i64 %s1, i64 5
%7 = insertelement <8 x i64> %5, i64 %s0, i64 7
%8 = insertelement <8 x i64> %6, i64 %s1, i64 7
%res = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %7, <8 x i64> %8, i8 0)
ret <8 x i64> %res
}
define <8 x i64> @test_demanded_elts_pclmulqdq_512_1(<8 x i64> %a0, <8 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_512_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0
; CHECK-NEXT: vpbroadcastq %rdi, %zmm2
; CHECK-NEXT: vmovdqa64 {{.*#+}} zmm3 = [u,1,u,11,u,13,u,15]
; CHECK-NEXT: vpermi2q %zmm2, %zmm0, %zmm3
; CHECK-NEXT: vpclmulqdq $1, %zmm1, %zmm3, %zmm0
; CHECK-NEXT: retq
%1 = insertelement <8 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <8 x i64> %a1, i64 %s1, i64 1
%3 = insertelement <8 x i64> %1, i64 %s0, i64 3
%4 = insertelement <8 x i64> %2, i64 %s1, i64 3
%5 = insertelement <8 x i64> %3, i64 %s0, i64 5
%6 = insertelement <8 x i64> %4, i64 %s1, i64 5
%7 = insertelement <8 x i64> %5, i64 %s0, i64 7
%8 = insertelement <8 x i64> %6, i64 %s1, i64 7
%res = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %7, <8 x i64> %8, i8 1)
ret <8 x i64> %res
}
define <8 x i64> @test_demanded_elts_pclmulqdq_512_16(<8 x i64> %a0, <8 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_512_16:
; CHECK: # %bb.0:
; CHECK-NEXT: vpinsrq $1, %rsi, %xmm0, %xmm1
; CHECK-NEXT: vpbroadcastq %rsi, %zmm2
; CHECK-NEXT: vmovdqa64 {{.*#+}} zmm3 = [u,1,u,11,u,13,u,15]
; CHECK-NEXT: vpermi2q %zmm2, %zmm1, %zmm3
; CHECK-NEXT: vpclmulqdq $16, %zmm3, %zmm0, %zmm0
; CHECK-NEXT: retq
%1 = insertelement <8 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <8 x i64> %a1, i64 %s1, i64 1
%3 = insertelement <8 x i64> %1, i64 %s0, i64 3
%4 = insertelement <8 x i64> %2, i64 %s1, i64 3
%5 = insertelement <8 x i64> %3, i64 %s0, i64 5
%6 = insertelement <8 x i64> %4, i64 %s1, i64 5
%7 = insertelement <8 x i64> %5, i64 %s0, i64 7
%8 = insertelement <8 x i64> %6, i64 %s1, i64 7
%res = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %7, <8 x i64> %8, i8 16)
ret <8 x i64> %res
}
define <8 x i64> @test_demanded_elts_pclmulqdq_512_17(<8 x i64> %a0, <8 x i64> %a1, i64 %s0, i64 %s1) {
; CHECK-LABEL: test_demanded_elts_pclmulqdq_512_17:
; CHECK: # %bb.0:
; CHECK-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0
; CHECK-NEXT: vpinsrq $1, %rsi, %xmm0, %xmm1
; CHECK-NEXT: vpbroadcastq %rdi, %zmm2
; CHECK-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,1,2,11,4,13,6,15]
; CHECK-NEXT: vpermt2q %zmm2, %zmm3, %zmm0
; CHECK-NEXT: vpbroadcastq %rsi, %zmm2
; CHECK-NEXT: vpermt2q %zmm2, %zmm3, %zmm1
; CHECK-NEXT: vpclmulqdq $17, %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
%1 = insertelement <8 x i64> %a0, i64 %s0, i64 1
%2 = insertelement <8 x i64> %a1, i64 %s1, i64 1
%3 = insertelement <8 x i64> %1, i64 %s0, i64 3
%4 = insertelement <8 x i64> %2, i64 %s1, i64 3
%5 = insertelement <8 x i64> %3, i64 %s0, i64 5
%6 = insertelement <8 x i64> %4, i64 %s1, i64 5
%7 = insertelement <8 x i64> %5, i64 %s0, i64 7
%8 = insertelement <8 x i64> %6, i64 %s1, i64 7
%res = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %7, <8 x i64> %8, i8 17)
ret <8 x i64> %res
}
; Ensure that target shuffle extraction can handle SM_SentinelZero.
define <2 x i64> @pclmul_sentinel_zero(<2 x i64> %a0, <2 x i64> %a1) {
; CHECK-LABEL: pclmul_sentinel_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%and = and <2 x i64> %a0, <i64 -1, i64 0>
%res = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %and, <2 x i64> %a1, i8 0)
ret <2 x i64> %res
}
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