derek.holloway
7502bf64a4
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39 lines
1.3 KiB
LLVM
39 lines
1.3 KiB
LLVM
; assert in DAGlegalizer with fake use of 1-element vectors.
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; RUN: llc -stop-after=finalize-isel -mtriple=x86_64-unknown-linux -filetype=asm -o - %s | FileCheck %s
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; ModuleID = 't2.cpp'
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; source_filename = "t2.cpp"
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; target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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;
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; Check that we get past ISel and generate FAKE_USE machine instructions for
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; one-element vectors.
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;
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; CHECK: bb.0.entry:
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; CHECK-DAG: %1:gr64 = COPY $rdi
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; CHECK-DAG: %0:vr128 = COPY $xmm0
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; CHECK: %2:vr64 =
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; CHECK-DAG: FAKE_USE %1
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; CHECK-DAG: FAKE_USE %0
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; CHECK: RET
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target triple = "x86_64-unknown-unknown"
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; Function Attrs: nounwind sspstrong uwtable
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define <4 x float> @_Z3runDv4_fDv1_x(<4 x float> %r, i64 %b.coerce) local_unnamed_addr #0 {
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entry:
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%0 = insertelement <1 x i64> undef, i64 %b.coerce, i32 0
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%1 = bitcast i64 %b.coerce to <1 x i64>
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%2 = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %r, <1 x i64> %1)
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tail call void (...) @llvm.fake.use(<1 x i64> %0)
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tail call void (...) @llvm.fake.use(<4 x float> %r)
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ret <4 x float> %2
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}
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, <1 x i64>)
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; Function Attrs: nounwind
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declare void @llvm.fake.use(...)
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attributes #0 = { "target-cpu"="btver2" optdebug }
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