derek.holloway
7502bf64a4
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914 lines
39 KiB
LLVM
914 lines
39 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s -check-prefixes=NOFMA
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+fma | FileCheck %s -check-prefixes=FMA3,FMA3_256
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+fma,+avx512f | FileCheck %s -check-prefixes=FMA3,FMA3_512
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+fma4 | FileCheck %s -check-prefixes=FMA4
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; This test checks the fusing of MUL + ADDSUB to FMADDSUB.
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define <2 x double> @mul_addsub_pd128(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
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; NOFMA-LABEL: mul_addsub_pd128:
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; NOFMA: # %bb.0: # %entry
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; NOFMA-NEXT: vmulpd %xmm1, %xmm0, %xmm0
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; NOFMA-NEXT: vaddsubpd %xmm2, %xmm0, %xmm0
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; NOFMA-NEXT: retq
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;
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; FMA3-LABEL: mul_addsub_pd128:
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; FMA3: # %bb.0: # %entry
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; FMA3-NEXT: vfmaddsub213pd {{.*#+}} xmm0 = (xmm1 * xmm0) +/- xmm2
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; FMA3-NEXT: retq
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;
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; FMA4-LABEL: mul_addsub_pd128:
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; FMA4: # %bb.0: # %entry
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; FMA4-NEXT: vfmaddsubpd {{.*#+}} xmm0 = (xmm0 * xmm1) +/- xmm2
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; FMA4-NEXT: retq
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entry:
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%AB = fmul contract <2 x double> %A, %B
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%Sub = fsub contract <2 x double> %AB, %C
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%Add = fadd contract <2 x double> %AB, %C
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%Addsub = shufflevector <2 x double> %Sub, <2 x double> %Add, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %Addsub
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}
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define <4 x float> @mul_addsub_ps128(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
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; NOFMA-LABEL: mul_addsub_ps128:
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; NOFMA: # %bb.0: # %entry
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; NOFMA-NEXT: vmulps %xmm1, %xmm0, %xmm0
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; NOFMA-NEXT: vaddsubps %xmm2, %xmm0, %xmm0
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; NOFMA-NEXT: retq
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;
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; FMA3-LABEL: mul_addsub_ps128:
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; FMA3: # %bb.0: # %entry
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; FMA3-NEXT: vfmaddsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) +/- xmm2
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; FMA3-NEXT: retq
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;
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; FMA4-LABEL: mul_addsub_ps128:
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; FMA4: # %bb.0: # %entry
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; FMA4-NEXT: vfmaddsubps {{.*#+}} xmm0 = (xmm0 * xmm1) +/- xmm2
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; FMA4-NEXT: retq
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entry:
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%AB = fmul contract <4 x float> %A, %B
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%Sub = fsub contract <4 x float> %AB, %C
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%Add = fadd contract <4 x float> %AB, %C
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%Addsub = shufflevector <4 x float> %Sub, <4 x float> %Add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %Addsub
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}
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define <4 x double> @mul_addsub_pd256(<4 x double> %A, <4 x double> %B, <4 x double> %C) {
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; NOFMA-LABEL: mul_addsub_pd256:
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; NOFMA: # %bb.0: # %entry
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; NOFMA-NEXT: vmulpd %ymm1, %ymm0, %ymm0
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; NOFMA-NEXT: vaddsubpd %ymm2, %ymm0, %ymm0
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; NOFMA-NEXT: retq
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;
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; FMA3-LABEL: mul_addsub_pd256:
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; FMA3: # %bb.0: # %entry
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; FMA3-NEXT: vfmaddsub213pd {{.*#+}} ymm0 = (ymm1 * ymm0) +/- ymm2
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; FMA3-NEXT: retq
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;
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; FMA4-LABEL: mul_addsub_pd256:
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; FMA4: # %bb.0: # %entry
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; FMA4-NEXT: vfmaddsubpd {{.*#+}} ymm0 = (ymm0 * ymm1) +/- ymm2
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; FMA4-NEXT: retq
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entry:
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%AB = fmul contract <4 x double> %A, %B
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%Sub = fsub contract <4 x double> %AB, %C
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%Add = fadd contract <4 x double> %AB, %C
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%Addsub = shufflevector <4 x double> %Sub, <4 x double> %Add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x double> %Addsub
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}
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define <8 x float> @mul_addsub_ps256(<8 x float> %A, <8 x float> %B, <8 x float> %C) {
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; NOFMA-LABEL: mul_addsub_ps256:
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; NOFMA: # %bb.0: # %entry
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; NOFMA-NEXT: vmulps %ymm1, %ymm0, %ymm0
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; NOFMA-NEXT: vaddsubps %ymm2, %ymm0, %ymm0
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; NOFMA-NEXT: retq
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;
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; FMA3-LABEL: mul_addsub_ps256:
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; FMA3: # %bb.0: # %entry
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; FMA3-NEXT: vfmaddsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) +/- ymm2
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; FMA3-NEXT: retq
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;
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; FMA4-LABEL: mul_addsub_ps256:
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; FMA4: # %bb.0: # %entry
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; FMA4-NEXT: vfmaddsubps {{.*#+}} ymm0 = (ymm0 * ymm1) +/- ymm2
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; FMA4-NEXT: retq
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entry:
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%AB = fmul contract <8 x float> %A, %B
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%Sub = fsub contract <8 x float> %AB, %C
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%Add = fadd contract <8 x float> %AB, %C
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%Addsub = shufflevector <8 x float> %Sub, <8 x float> %Add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x float> %Addsub
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}
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define <8 x double> @mul_addsub_pd512(<8 x double> %A, <8 x double> %B, <8 x double> %C) {
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; NOFMA-LABEL: mul_addsub_pd512:
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; NOFMA: # %bb.0: # %entry
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; NOFMA-NEXT: vmulpd %ymm3, %ymm1, %ymm1
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; NOFMA-NEXT: vmulpd %ymm2, %ymm0, %ymm0
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; NOFMA-NEXT: vaddsubpd %ymm4, %ymm0, %ymm0
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; NOFMA-NEXT: vaddsubpd %ymm5, %ymm1, %ymm1
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; NOFMA-NEXT: retq
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;
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; FMA3_256-LABEL: mul_addsub_pd512:
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; FMA3_256: # %bb.0: # %entry
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; FMA3_256-NEXT: vfmaddsub213pd {{.*#+}} ymm0 = (ymm2 * ymm0) +/- ymm4
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; FMA3_256-NEXT: vfmaddsub213pd {{.*#+}} ymm1 = (ymm3 * ymm1) +/- ymm5
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; FMA3_256-NEXT: retq
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;
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; FMA3_512-LABEL: mul_addsub_pd512:
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; FMA3_512: # %bb.0: # %entry
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; FMA3_512-NEXT: vfmaddsub213pd {{.*#+}} zmm0 = (zmm1 * zmm0) +/- zmm2
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; FMA3_512-NEXT: retq
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;
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; FMA4-LABEL: mul_addsub_pd512:
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; FMA4: # %bb.0: # %entry
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; FMA4-NEXT: vfmaddsubpd {{.*#+}} ymm0 = (ymm0 * ymm2) +/- ymm4
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; FMA4-NEXT: vfmaddsubpd {{.*#+}} ymm1 = (ymm1 * ymm3) +/- ymm5
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; FMA4-NEXT: retq
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entry:
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%AB = fmul contract <8 x double> %A, %B
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%Sub = fsub contract <8 x double> %AB, %C
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%Add = fadd contract <8 x double> %AB, %C
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%Addsub = shufflevector <8 x double> %Sub, <8 x double> %Add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x double> %Addsub
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}
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define <16 x float> @mul_addsub_ps512(<16 x float> %A, <16 x float> %B, <16 x float> %C) {
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; NOFMA-LABEL: mul_addsub_ps512:
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; NOFMA: # %bb.0: # %entry
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; NOFMA-NEXT: vmulps %ymm3, %ymm1, %ymm1
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; NOFMA-NEXT: vmulps %ymm2, %ymm0, %ymm0
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; NOFMA-NEXT: vaddsubps %ymm4, %ymm0, %ymm0
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; NOFMA-NEXT: vaddsubps %ymm5, %ymm1, %ymm1
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; NOFMA-NEXT: retq
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;
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; FMA3_256-LABEL: mul_addsub_ps512:
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; FMA3_256: # %bb.0: # %entry
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; FMA3_256-NEXT: vfmaddsub213ps {{.*#+}} ymm0 = (ymm2 * ymm0) +/- ymm4
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; FMA3_256-NEXT: vfmaddsub213ps {{.*#+}} ymm1 = (ymm3 * ymm1) +/- ymm5
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; FMA3_256-NEXT: retq
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;
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; FMA3_512-LABEL: mul_addsub_ps512:
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; FMA3_512: # %bb.0: # %entry
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; FMA3_512-NEXT: vfmaddsub213ps {{.*#+}} zmm0 = (zmm1 * zmm0) +/- zmm2
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; FMA3_512-NEXT: retq
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;
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; FMA4-LABEL: mul_addsub_ps512:
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; FMA4: # %bb.0: # %entry
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; FMA4-NEXT: vfmaddsubps {{.*#+}} ymm0 = (ymm0 * ymm2) +/- ymm4
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; FMA4-NEXT: vfmaddsubps {{.*#+}} ymm1 = (ymm1 * ymm3) +/- ymm5
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; FMA4-NEXT: retq
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entry:
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%AB = fmul contract <16 x float> %A, %B
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%Sub = fsub contract <16 x float> %AB, %C
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%Add = fadd contract <16 x float> %AB, %C
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%Addsub = shufflevector <16 x float> %Sub, <16 x float> %Add, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
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ret <16 x float> %Addsub
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}
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define <4 x float> @buildvector_mul_addsub_ps128(<4 x float> %C, <4 x float> %D, <4 x float> %B) {
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; NOFMA-LABEL: buildvector_mul_addsub_ps128:
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; NOFMA: # %bb.0: # %bb
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; NOFMA-NEXT: vmulps %xmm1, %xmm0, %xmm0
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; NOFMA-NEXT: vaddsubps %xmm2, %xmm0, %xmm0
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; NOFMA-NEXT: retq
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;
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; FMA3-LABEL: buildvector_mul_addsub_ps128:
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; FMA3: # %bb.0: # %bb
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; FMA3-NEXT: vfmaddsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) +/- xmm2
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; FMA3-NEXT: retq
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;
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; FMA4-LABEL: buildvector_mul_addsub_ps128:
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; FMA4: # %bb.0: # %bb
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; FMA4-NEXT: vfmaddsubps {{.*#+}} xmm0 = (xmm0 * xmm1) +/- xmm2
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; FMA4-NEXT: retq
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bb:
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%A = fmul contract <4 x float> %C, %D
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%A0 = extractelement <4 x float> %A, i32 0
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%B0 = extractelement <4 x float> %B, i32 0
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%sub0 = fsub contract float %A0, %B0
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%A2 = extractelement <4 x float> %A, i32 2
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%B2 = extractelement <4 x float> %B, i32 2
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%sub2 = fsub contract float %A2, %B2
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%A1 = extractelement <4 x float> %A, i32 1
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%B1 = extractelement <4 x float> %B, i32 1
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%add1 = fadd contract float %A1, %B1
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%A3 = extractelement <4 x float> %A, i32 3
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%B3 = extractelement <4 x float> %B, i32 3
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%add3 = fadd contract float %A3, %B3
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%vecinsert1 = insertelement <4 x float> undef, float %sub0, i32 0
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%vecinsert2 = insertelement <4 x float> %vecinsert1, float %add1, i32 1
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%vecinsert3 = insertelement <4 x float> %vecinsert2, float %sub2, i32 2
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%vecinsert4 = insertelement <4 x float> %vecinsert3, float %add3, i32 3
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ret <4 x float> %vecinsert4
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}
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define <2 x double> @buildvector_mul_addsub_pd128(<2 x double> %C, <2 x double> %D, <2 x double> %B) {
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; NOFMA-LABEL: buildvector_mul_addsub_pd128:
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; NOFMA: # %bb.0: # %bb
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; NOFMA-NEXT: vmulpd %xmm1, %xmm0, %xmm0
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; NOFMA-NEXT: vaddsubpd %xmm2, %xmm0, %xmm0
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; NOFMA-NEXT: retq
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;
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; FMA3-LABEL: buildvector_mul_addsub_pd128:
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; FMA3: # %bb.0: # %bb
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; FMA3-NEXT: vfmaddsub213pd {{.*#+}} xmm0 = (xmm1 * xmm0) +/- xmm2
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; FMA3-NEXT: retq
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;
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; FMA4-LABEL: buildvector_mul_addsub_pd128:
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; FMA4: # %bb.0: # %bb
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; FMA4-NEXT: vfmaddsubpd {{.*#+}} xmm0 = (xmm0 * xmm1) +/- xmm2
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; FMA4-NEXT: retq
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bb:
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%A = fmul contract <2 x double> %C, %D
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%A0 = extractelement <2 x double> %A, i32 0
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%B0 = extractelement <2 x double> %B, i32 0
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%sub0 = fsub contract double %A0, %B0
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%A1 = extractelement <2 x double> %A, i32 1
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%B1 = extractelement <2 x double> %B, i32 1
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%add1 = fadd contract double %A1, %B1
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%vecinsert1 = insertelement <2 x double> undef, double %sub0, i32 0
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%vecinsert2 = insertelement <2 x double> %vecinsert1, double %add1, i32 1
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ret <2 x double> %vecinsert2
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}
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define <8 x float> @buildvector_mul_addsub_ps256(<8 x float> %C, <8 x float> %D, <8 x float> %B) {
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; NOFMA-LABEL: buildvector_mul_addsub_ps256:
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; NOFMA: # %bb.0: # %bb
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; NOFMA-NEXT: vmulps %ymm1, %ymm0, %ymm0
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; NOFMA-NEXT: vaddsubps %ymm2, %ymm0, %ymm0
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; NOFMA-NEXT: retq
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;
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; FMA3-LABEL: buildvector_mul_addsub_ps256:
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; FMA3: # %bb.0: # %bb
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; FMA3-NEXT: vfmaddsub213ps {{.*#+}} ymm0 = (ymm1 * ymm0) +/- ymm2
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; FMA3-NEXT: retq
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;
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; FMA4-LABEL: buildvector_mul_addsub_ps256:
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; FMA4: # %bb.0: # %bb
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; FMA4-NEXT: vfmaddsubps {{.*#+}} ymm0 = (ymm0 * ymm1) +/- ymm2
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; FMA4-NEXT: retq
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bb:
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%A = fmul contract <8 x float> %C, %D
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%A0 = extractelement <8 x float> %A, i32 0
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%B0 = extractelement <8 x float> %B, i32 0
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%sub0 = fsub contract float %A0, %B0
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%A2 = extractelement <8 x float> %A, i32 2
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%B2 = extractelement <8 x float> %B, i32 2
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%sub2 = fsub contract float %A2, %B2
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%A4 = extractelement <8 x float> %A, i32 4
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%B4 = extractelement <8 x float> %B, i32 4
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%sub4 = fsub contract float %A4, %B4
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%A6 = extractelement <8 x float> %A, i32 6
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%B6 = extractelement <8 x float> %B, i32 6
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%sub6 = fsub contract float %A6, %B6
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%A1 = extractelement <8 x float> %A, i32 1
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%B1 = extractelement <8 x float> %B, i32 1
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%add1 = fadd contract float %A1, %B1
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%A3 = extractelement <8 x float> %A, i32 3
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%B3 = extractelement <8 x float> %B, i32 3
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%add3 = fadd contract float %A3, %B3
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%A5 = extractelement <8 x float> %A, i32 5
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%B5 = extractelement <8 x float> %B, i32 5
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%add5 = fadd contract float %A5, %B5
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%A7 = extractelement <8 x float> %A, i32 7
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%B7 = extractelement <8 x float> %B, i32 7
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%add7 = fadd contract float %A7, %B7
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%vecinsert1 = insertelement <8 x float> undef, float %sub0, i32 0
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%vecinsert2 = insertelement <8 x float> %vecinsert1, float %add1, i32 1
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%vecinsert3 = insertelement <8 x float> %vecinsert2, float %sub2, i32 2
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%vecinsert4 = insertelement <8 x float> %vecinsert3, float %add3, i32 3
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%vecinsert5 = insertelement <8 x float> %vecinsert4, float %sub4, i32 4
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%vecinsert6 = insertelement <8 x float> %vecinsert5, float %add5, i32 5
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%vecinsert7 = insertelement <8 x float> %vecinsert6, float %sub6, i32 6
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%vecinsert8 = insertelement <8 x float> %vecinsert7, float %add7, i32 7
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|
ret <8 x float> %vecinsert8
|
|
}
|
|
|
|
define <4 x double> @buildvector_mul_addsub_pd256(<4 x double> %C, <4 x double> %D, <4 x double> %B) {
|
|
; NOFMA-LABEL: buildvector_mul_addsub_pd256:
|
|
; NOFMA: # %bb.0: # %bb
|
|
; NOFMA-NEXT: vmulpd %ymm1, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vaddsubpd %ymm2, %ymm0, %ymm0
|
|
; NOFMA-NEXT: retq
|
|
;
|
|
; FMA3-LABEL: buildvector_mul_addsub_pd256:
|
|
; FMA3: # %bb.0: # %bb
|
|
; FMA3-NEXT: vfmaddsub213pd {{.*#+}} ymm0 = (ymm1 * ymm0) +/- ymm2
|
|
; FMA3-NEXT: retq
|
|
;
|
|
; FMA4-LABEL: buildvector_mul_addsub_pd256:
|
|
; FMA4: # %bb.0: # %bb
|
|
; FMA4-NEXT: vfmaddsubpd {{.*#+}} ymm0 = (ymm0 * ymm1) +/- ymm2
|
|
; FMA4-NEXT: retq
|
|
bb:
|
|
%A = fmul contract <4 x double> %C, %D
|
|
%A0 = extractelement <4 x double> %A, i32 0
|
|
%B0 = extractelement <4 x double> %B, i32 0
|
|
%sub0 = fsub contract double %A0, %B0
|
|
%A2 = extractelement <4 x double> %A, i32 2
|
|
%B2 = extractelement <4 x double> %B, i32 2
|
|
%sub2 = fsub contract double %A2, %B2
|
|
%A1 = extractelement <4 x double> %A, i32 1
|
|
%B1 = extractelement <4 x double> %B, i32 1
|
|
%add1 = fadd contract double %A1, %B1
|
|
%A3 = extractelement <4 x double> %A, i32 3
|
|
%B3 = extractelement <4 x double> %B, i32 3
|
|
%add3 = fadd contract double %A3, %B3
|
|
%vecinsert1 = insertelement <4 x double> undef, double %sub0, i32 0
|
|
%vecinsert2 = insertelement <4 x double> %vecinsert1, double %add1, i32 1
|
|
%vecinsert3 = insertelement <4 x double> %vecinsert2, double %sub2, i32 2
|
|
%vecinsert4 = insertelement <4 x double> %vecinsert3, double %add3, i32 3
|
|
ret <4 x double> %vecinsert4
|
|
}
|
|
|
|
define <16 x float> @buildvector_mul_addsub_ps512(<16 x float> %C, <16 x float> %D, <16 x float> %B) {
|
|
; NOFMA-LABEL: buildvector_mul_addsub_ps512:
|
|
; NOFMA: # %bb.0: # %bb
|
|
; NOFMA-NEXT: vmulps %ymm3, %ymm1, %ymm1
|
|
; NOFMA-NEXT: vmulps %ymm2, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vaddsubps %ymm4, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vaddsubps %ymm5, %ymm1, %ymm1
|
|
; NOFMA-NEXT: retq
|
|
;
|
|
; FMA3_256-LABEL: buildvector_mul_addsub_ps512:
|
|
; FMA3_256: # %bb.0: # %bb
|
|
; FMA3_256-NEXT: vfmaddsub213ps {{.*#+}} ymm0 = (ymm2 * ymm0) +/- ymm4
|
|
; FMA3_256-NEXT: vfmaddsub213ps {{.*#+}} ymm1 = (ymm3 * ymm1) +/- ymm5
|
|
; FMA3_256-NEXT: retq
|
|
;
|
|
; FMA3_512-LABEL: buildvector_mul_addsub_ps512:
|
|
; FMA3_512: # %bb.0: # %bb
|
|
; FMA3_512-NEXT: vfmaddsub213ps {{.*#+}} zmm0 = (zmm1 * zmm0) +/- zmm2
|
|
; FMA3_512-NEXT: retq
|
|
;
|
|
; FMA4-LABEL: buildvector_mul_addsub_ps512:
|
|
; FMA4: # %bb.0: # %bb
|
|
; FMA4-NEXT: vfmaddsubps {{.*#+}} ymm0 = (ymm0 * ymm2) +/- ymm4
|
|
; FMA4-NEXT: vfmaddsubps {{.*#+}} ymm1 = (ymm1 * ymm3) +/- ymm5
|
|
; FMA4-NEXT: retq
|
|
bb:
|
|
%A = fmul contract <16 x float> %C, %D
|
|
%A0 = extractelement <16 x float> %A, i32 0
|
|
%B0 = extractelement <16 x float> %B, i32 0
|
|
%sub0 = fsub contract float %A0, %B0
|
|
%A2 = extractelement <16 x float> %A, i32 2
|
|
%B2 = extractelement <16 x float> %B, i32 2
|
|
%sub2 = fsub contract float %A2, %B2
|
|
%A4 = extractelement <16 x float> %A, i32 4
|
|
%B4 = extractelement <16 x float> %B, i32 4
|
|
%sub4 = fsub contract float %A4, %B4
|
|
%A6 = extractelement <16 x float> %A, i32 6
|
|
%B6 = extractelement <16 x float> %B, i32 6
|
|
%sub6 = fsub contract float %A6, %B6
|
|
%A8 = extractelement <16 x float> %A, i32 8
|
|
%B8 = extractelement <16 x float> %B, i32 8
|
|
%sub8 = fsub contract float %A8, %B8
|
|
%A10 = extractelement <16 x float> %A, i32 10
|
|
%B10 = extractelement <16 x float> %B, i32 10
|
|
%sub10 = fsub contract float %A10, %B10
|
|
%A12 = extractelement <16 x float> %A, i32 12
|
|
%B12 = extractelement <16 x float> %B, i32 12
|
|
%sub12 = fsub contract float %A12, %B12
|
|
%A14 = extractelement <16 x float> %A, i32 14
|
|
%B14 = extractelement <16 x float> %B, i32 14
|
|
%sub14 = fsub contract float %A14, %B14
|
|
%A1 = extractelement <16 x float> %A, i32 1
|
|
%B1 = extractelement <16 x float> %B, i32 1
|
|
%add1 = fadd contract float %A1, %B1
|
|
%A3 = extractelement <16 x float> %A, i32 3
|
|
%B3 = extractelement <16 x float> %B, i32 3
|
|
%add3 = fadd contract float %A3, %B3
|
|
%A5 = extractelement <16 x float> %A, i32 5
|
|
%B5 = extractelement <16 x float> %B, i32 5
|
|
%add5 = fadd contract float %A5, %B5
|
|
%A7 = extractelement <16 x float> %A, i32 7
|
|
%B7 = extractelement <16 x float> %B, i32 7
|
|
%add7 = fadd contract float %A7, %B7
|
|
%A9 = extractelement <16 x float> %A, i32 9
|
|
%B9 = extractelement <16 x float> %B, i32 9
|
|
%add9 = fadd contract float %A9, %B9
|
|
%A11 = extractelement <16 x float> %A, i32 11
|
|
%B11 = extractelement <16 x float> %B, i32 11
|
|
%add11 = fadd contract float %A11, %B11
|
|
%A13 = extractelement <16 x float> %A, i32 13
|
|
%B13 = extractelement <16 x float> %B, i32 13
|
|
%add13 = fadd contract float %A13, %B13
|
|
%A15 = extractelement <16 x float> %A, i32 15
|
|
%B15 = extractelement <16 x float> %B, i32 15
|
|
%add15 = fadd contract float %A15, %B15
|
|
%vecinsert1 = insertelement <16 x float> undef, float %sub0, i32 0
|
|
%vecinsert2 = insertelement <16 x float> %vecinsert1, float %add1, i32 1
|
|
%vecinsert3 = insertelement <16 x float> %vecinsert2, float %sub2, i32 2
|
|
%vecinsert4 = insertelement <16 x float> %vecinsert3, float %add3, i32 3
|
|
%vecinsert5 = insertelement <16 x float> %vecinsert4, float %sub4, i32 4
|
|
; element 5 is undef
|
|
%vecinsert7 = insertelement <16 x float> %vecinsert5, float %sub6, i32 6
|
|
%vecinsert8 = insertelement <16 x float> %vecinsert7, float %add7, i32 7
|
|
%vecinsert9 = insertelement <16 x float> %vecinsert8, float %sub8, i32 8
|
|
%vecinsert10 = insertelement <16 x float> %vecinsert9, float %add9, i32 9
|
|
%vecinsert11 = insertelement <16 x float> %vecinsert10, float %sub10, i32 10
|
|
%vecinsert12 = insertelement <16 x float> %vecinsert11, float %add11, i32 11
|
|
; element 12 is undef
|
|
%vecinsert14 = insertelement <16 x float> %vecinsert12, float %add13, i32 13
|
|
%vecinsert15 = insertelement <16 x float> %vecinsert14, float %sub14, i32 14
|
|
%vecinsert16 = insertelement <16 x float> %vecinsert15, float %add15, i32 15
|
|
ret <16 x float> %vecinsert16
|
|
}
|
|
|
|
define <8 x double> @buildvector_mul_addsub_pd512(<8 x double> %C, <8 x double> %D, <8 x double> %B) {
|
|
; NOFMA-LABEL: buildvector_mul_addsub_pd512:
|
|
; NOFMA: # %bb.0: # %bb
|
|
; NOFMA-NEXT: vmulpd %ymm3, %ymm1, %ymm1
|
|
; NOFMA-NEXT: vmulpd %ymm2, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vaddsubpd %ymm4, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vaddsubpd %ymm5, %ymm1, %ymm1
|
|
; NOFMA-NEXT: retq
|
|
;
|
|
; FMA3_256-LABEL: buildvector_mul_addsub_pd512:
|
|
; FMA3_256: # %bb.0: # %bb
|
|
; FMA3_256-NEXT: vfmaddsub213pd {{.*#+}} ymm0 = (ymm2 * ymm0) +/- ymm4
|
|
; FMA3_256-NEXT: vfmaddsub213pd {{.*#+}} ymm1 = (ymm3 * ymm1) +/- ymm5
|
|
; FMA3_256-NEXT: retq
|
|
;
|
|
; FMA3_512-LABEL: buildvector_mul_addsub_pd512:
|
|
; FMA3_512: # %bb.0: # %bb
|
|
; FMA3_512-NEXT: vfmaddsub213pd {{.*#+}} zmm0 = (zmm1 * zmm0) +/- zmm2
|
|
; FMA3_512-NEXT: retq
|
|
;
|
|
; FMA4-LABEL: buildvector_mul_addsub_pd512:
|
|
; FMA4: # %bb.0: # %bb
|
|
; FMA4-NEXT: vfmaddsubpd {{.*#+}} ymm0 = (ymm0 * ymm2) +/- ymm4
|
|
; FMA4-NEXT: vfmaddsubpd {{.*#+}} ymm1 = (ymm1 * ymm3) +/- ymm5
|
|
; FMA4-NEXT: retq
|
|
bb:
|
|
%A = fmul contract <8 x double> %C, %D
|
|
%A0 = extractelement <8 x double> %A, i32 0
|
|
%B0 = extractelement <8 x double> %B, i32 0
|
|
%sub0 = fsub contract double %A0, %B0
|
|
%A2 = extractelement <8 x double> %A, i32 2
|
|
%B2 = extractelement <8 x double> %B, i32 2
|
|
%sub2 = fsub contract double %A2, %B2
|
|
%A4 = extractelement <8 x double> %A, i32 4
|
|
%B4 = extractelement <8 x double> %B, i32 4
|
|
%sub4 = fsub contract double %A4, %B4
|
|
%A6 = extractelement <8 x double> %A, i32 6
|
|
%B6 = extractelement <8 x double> %B, i32 6
|
|
%sub6 = fsub contract double %A6, %B6
|
|
%A1 = extractelement <8 x double> %A, i32 1
|
|
%B1 = extractelement <8 x double> %B, i32 1
|
|
%add1 = fadd contract double %A1, %B1
|
|
%A3 = extractelement <8 x double> %A, i32 3
|
|
%B3 = extractelement <8 x double> %B, i32 3
|
|
%add3 = fadd contract double %A3, %B3
|
|
%A7 = extractelement <8 x double> %A, i32 7
|
|
%B7 = extractelement <8 x double> %B, i32 7
|
|
%add7 = fadd contract double %A7, %B7
|
|
%vecinsert1 = insertelement <8 x double> undef, double %sub0, i32 0
|
|
%vecinsert2 = insertelement <8 x double> %vecinsert1, double %add1, i32 1
|
|
%vecinsert3 = insertelement <8 x double> %vecinsert2, double %sub2, i32 2
|
|
%vecinsert4 = insertelement <8 x double> %vecinsert3, double %add3, i32 3
|
|
%vecinsert5 = insertelement <8 x double> %vecinsert4, double %sub4, i32 4
|
|
; element 5 is undef
|
|
%vecinsert7 = insertelement <8 x double> %vecinsert5, double %sub6, i32 6
|
|
%vecinsert8 = insertelement <8 x double> %vecinsert7, double %add7, i32 7
|
|
ret <8 x double> %vecinsert8
|
|
}
|
|
|
|
define <4 x float> @buildvector_mul_subadd_ps128(<4 x float> %C, <4 x float> %D, <4 x float> %B) {
|
|
; NOFMA-LABEL: buildvector_mul_subadd_ps128:
|
|
; NOFMA: # %bb.0: # %bb
|
|
; NOFMA-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
|
; NOFMA-NEXT: vaddss %xmm2, %xmm0, %xmm1
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm4 = xmm2[1,0]
|
|
; NOFMA-NEXT: vaddss %xmm4, %xmm3, %xmm3
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm5 = xmm2[1,1,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm5, %xmm4, %xmm4
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[2,3]
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm2, %xmm0, %xmm0
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
|
|
; NOFMA-NEXT: retq
|
|
;
|
|
; FMA3-LABEL: buildvector_mul_subadd_ps128:
|
|
; FMA3: # %bb.0: # %bb
|
|
; FMA3-NEXT: vfmsubadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) -/+ xmm2
|
|
; FMA3-NEXT: retq
|
|
;
|
|
; FMA4-LABEL: buildvector_mul_subadd_ps128:
|
|
; FMA4: # %bb.0: # %bb
|
|
; FMA4-NEXT: vfmsubaddps {{.*#+}} xmm0 = (xmm0 * xmm1) -/+ xmm2
|
|
; FMA4-NEXT: retq
|
|
bb:
|
|
%A = fmul contract <4 x float> %C, %D
|
|
%A0 = extractelement <4 x float> %A, i32 0
|
|
%B0 = extractelement <4 x float> %B, i32 0
|
|
%sub0 = fadd contract float %A0, %B0
|
|
%A2 = extractelement <4 x float> %A, i32 2
|
|
%B2 = extractelement <4 x float> %B, i32 2
|
|
%sub2 = fadd contract float %A2, %B2
|
|
%A1 = extractelement <4 x float> %A, i32 1
|
|
%B1 = extractelement <4 x float> %B, i32 1
|
|
%add1 = fsub contract float %A1, %B1
|
|
%A3 = extractelement <4 x float> %A, i32 3
|
|
%B3 = extractelement <4 x float> %B, i32 3
|
|
%add3 = fsub contract float %A3, %B3
|
|
%vecinsert1 = insertelement <4 x float> undef, float %sub0, i32 0
|
|
%vecinsert2 = insertelement <4 x float> %vecinsert1, float %add1, i32 1
|
|
%vecinsert3 = insertelement <4 x float> %vecinsert2, float %sub2, i32 2
|
|
%vecinsert4 = insertelement <4 x float> %vecinsert3, float %add3, i32 3
|
|
ret <4 x float> %vecinsert4
|
|
}
|
|
|
|
define <2 x double> @buildvector_mul_subadd_pd128(<2 x double> %C, <2 x double> %D, <2 x double> %B) {
|
|
; NOFMA-LABEL: buildvector_mul_subadd_pd128:
|
|
; NOFMA: # %bb.0: # %bb
|
|
; NOFMA-NEXT: vmulpd %xmm1, %xmm0, %xmm0
|
|
; NOFMA-NEXT: vaddsd %xmm2, %xmm0, %xmm1
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
|
|
; NOFMA-NEXT: vsubsd %xmm2, %xmm0, %xmm0
|
|
; NOFMA-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
|
|
; NOFMA-NEXT: retq
|
|
;
|
|
; FMA3-LABEL: buildvector_mul_subadd_pd128:
|
|
; FMA3: # %bb.0: # %bb
|
|
; FMA3-NEXT: vfmsubadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) -/+ xmm2
|
|
; FMA3-NEXT: retq
|
|
;
|
|
; FMA4-LABEL: buildvector_mul_subadd_pd128:
|
|
; FMA4: # %bb.0: # %bb
|
|
; FMA4-NEXT: vfmsubaddpd {{.*#+}} xmm0 = (xmm0 * xmm1) -/+ xmm2
|
|
; FMA4-NEXT: retq
|
|
bb:
|
|
%A = fmul contract <2 x double> %C, %D
|
|
%A0 = extractelement <2 x double> %A, i32 0
|
|
%B0 = extractelement <2 x double> %B, i32 0
|
|
%sub0 = fadd contract double %A0, %B0
|
|
%A1 = extractelement <2 x double> %A, i32 1
|
|
%B1 = extractelement <2 x double> %B, i32 1
|
|
%add1 = fsub contract double %A1, %B1
|
|
%vecinsert1 = insertelement <2 x double> undef, double %sub0, i32 0
|
|
%vecinsert2 = insertelement <2 x double> %vecinsert1, double %add1, i32 1
|
|
ret <2 x double> %vecinsert2
|
|
}
|
|
|
|
define <8 x float> @buildvector_mul_subadd_ps256(<8 x float> %C, <8 x float> %D, <8 x float> %B) {
|
|
; NOFMA-LABEL: buildvector_mul_subadd_ps256:
|
|
; NOFMA: # %bb.0: # %bb
|
|
; NOFMA-NEXT: vmulps %ymm1, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vaddss %xmm2, %xmm0, %xmm1
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm4 = xmm2[1,0]
|
|
; NOFMA-NEXT: vaddss %xmm4, %xmm3, %xmm3
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm0, %xmm4
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm2, %xmm5
|
|
; NOFMA-NEXT: vaddss %xmm5, %xmm4, %xmm6
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm7 = xmm4[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm8 = xmm5[1,0]
|
|
; NOFMA-NEXT: vaddss %xmm7, %xmm8, %xmm7
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm8 = xmm0[1,1,3,3]
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm9 = xmm2[1,1,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm9, %xmm8, %xmm8
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm8[0],xmm1[2,3]
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm2 = xmm2[3,3,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm2, %xmm0, %xmm0
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm1 = xmm4[1,1,3,3]
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm2 = xmm5[1,1,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm2, %xmm1, %xmm1
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm6[0],xmm1[0],xmm6[2,3]
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm7[0],xmm1[3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm2 = xmm4[3,3,3,3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm3 = xmm5[3,3,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm3, %xmm2, %xmm2
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
|
|
; NOFMA-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
|
; NOFMA-NEXT: retq
|
|
;
|
|
; FMA3-LABEL: buildvector_mul_subadd_ps256:
|
|
; FMA3: # %bb.0: # %bb
|
|
; FMA3-NEXT: vfmsubadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm2
|
|
; FMA3-NEXT: retq
|
|
;
|
|
; FMA4-LABEL: buildvector_mul_subadd_ps256:
|
|
; FMA4: # %bb.0: # %bb
|
|
; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm0 = (ymm0 * ymm1) -/+ ymm2
|
|
; FMA4-NEXT: retq
|
|
bb:
|
|
%A = fmul contract <8 x float> %C, %D
|
|
%A0 = extractelement <8 x float> %A, i32 0
|
|
%B0 = extractelement <8 x float> %B, i32 0
|
|
%sub0 = fadd contract float %A0, %B0
|
|
%A2 = extractelement <8 x float> %A, i32 2
|
|
%B2 = extractelement <8 x float> %B, i32 2
|
|
%sub2 = fadd contract float %A2, %B2
|
|
%A4 = extractelement <8 x float> %A, i32 4
|
|
%B4 = extractelement <8 x float> %B, i32 4
|
|
%sub4 = fadd contract float %A4, %B4
|
|
%A6 = extractelement <8 x float> %A, i32 6
|
|
%B6 = extractelement <8 x float> %B, i32 6
|
|
%sub6 = fadd contract float %A6, %B6
|
|
%A1 = extractelement <8 x float> %A, i32 1
|
|
%B1 = extractelement <8 x float> %B, i32 1
|
|
%add1 = fsub contract float %A1, %B1
|
|
%A3 = extractelement <8 x float> %A, i32 3
|
|
%B3 = extractelement <8 x float> %B, i32 3
|
|
%add3 = fsub contract float %A3, %B3
|
|
%A5 = extractelement <8 x float> %A, i32 5
|
|
%B5 = extractelement <8 x float> %B, i32 5
|
|
%add5 = fsub contract float %A5, %B5
|
|
%A7 = extractelement <8 x float> %A, i32 7
|
|
%B7 = extractelement <8 x float> %B, i32 7
|
|
%add7 = fsub contract float %A7, %B7
|
|
%vecinsert1 = insertelement <8 x float> undef, float %sub0, i32 0
|
|
%vecinsert2 = insertelement <8 x float> %vecinsert1, float %add1, i32 1
|
|
%vecinsert3 = insertelement <8 x float> %vecinsert2, float %sub2, i32 2
|
|
%vecinsert4 = insertelement <8 x float> %vecinsert3, float %add3, i32 3
|
|
%vecinsert5 = insertelement <8 x float> %vecinsert4, float %sub4, i32 4
|
|
%vecinsert6 = insertelement <8 x float> %vecinsert5, float %add5, i32 5
|
|
%vecinsert7 = insertelement <8 x float> %vecinsert6, float %sub6, i32 6
|
|
%vecinsert8 = insertelement <8 x float> %vecinsert7, float %add7, i32 7
|
|
ret <8 x float> %vecinsert8
|
|
}
|
|
|
|
define <4 x double> @buildvector_mul_subadd_pd256(<4 x double> %C, <4 x double> %D, <4 x double> %B) {
|
|
; NOFMA-LABEL: buildvector_mul_subadd_pd256:
|
|
; NOFMA: # %bb.0: # %bb
|
|
; NOFMA-NEXT: vmulpd %ymm1, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vaddsd %xmm2, %xmm0, %xmm1
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm0, %xmm3
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm2, %xmm4
|
|
; NOFMA-NEXT: vaddsd %xmm4, %xmm3, %xmm5
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
|
|
; NOFMA-NEXT: vsubsd %xmm2, %xmm0, %xmm0
|
|
; NOFMA-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm1 = xmm3[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm2 = xmm4[1,0]
|
|
; NOFMA-NEXT: vsubsd %xmm2, %xmm1, %xmm1
|
|
; NOFMA-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm5[0],xmm1[0]
|
|
; NOFMA-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
|
; NOFMA-NEXT: retq
|
|
;
|
|
; FMA3-LABEL: buildvector_mul_subadd_pd256:
|
|
; FMA3: # %bb.0: # %bb
|
|
; FMA3-NEXT: vfmsubadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) -/+ ymm2
|
|
; FMA3-NEXT: retq
|
|
;
|
|
; FMA4-LABEL: buildvector_mul_subadd_pd256:
|
|
; FMA4: # %bb.0: # %bb
|
|
; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm0 = (ymm0 * ymm1) -/+ ymm2
|
|
; FMA4-NEXT: retq
|
|
bb:
|
|
%A = fmul contract <4 x double> %C, %D
|
|
%A0 = extractelement <4 x double> %A, i32 0
|
|
%B0 = extractelement <4 x double> %B, i32 0
|
|
%sub0 = fadd contract double %A0, %B0
|
|
%A2 = extractelement <4 x double> %A, i32 2
|
|
%B2 = extractelement <4 x double> %B, i32 2
|
|
%sub2 = fadd contract double %A2, %B2
|
|
%A1 = extractelement <4 x double> %A, i32 1
|
|
%B1 = extractelement <4 x double> %B, i32 1
|
|
%add1 = fsub contract double %A1, %B1
|
|
%A3 = extractelement <4 x double> %A, i32 3
|
|
%B3 = extractelement <4 x double> %B, i32 3
|
|
%add3 = fsub contract double %A3, %B3
|
|
%vecinsert1 = insertelement <4 x double> undef, double %sub0, i32 0
|
|
%vecinsert2 = insertelement <4 x double> %vecinsert1, double %add1, i32 1
|
|
%vecinsert3 = insertelement <4 x double> %vecinsert2, double %sub2, i32 2
|
|
%vecinsert4 = insertelement <4 x double> %vecinsert3, double %add3, i32 3
|
|
ret <4 x double> %vecinsert4
|
|
}
|
|
|
|
define <16 x float> @buildvector_mul_subadd_ps512(<16 x float> %C, <16 x float> %D, <16 x float> %B) {
|
|
; NOFMA-LABEL: buildvector_mul_subadd_ps512:
|
|
; NOFMA: # %bb.0: # %bb
|
|
; NOFMA-NEXT: vmulps %ymm3, %ymm1, %ymm1
|
|
; NOFMA-NEXT: vmulps %ymm2, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vaddss %xmm4, %xmm0, %xmm2
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm6 = xmm4[1,0]
|
|
; NOFMA-NEXT: vaddss %xmm6, %xmm3, %xmm3
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm0, %xmm6
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm4, %xmm7
|
|
; NOFMA-NEXT: vaddss %xmm7, %xmm6, %xmm8
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm9 = xmm6[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm10 = xmm7[1,0]
|
|
; NOFMA-NEXT: vaddss %xmm10, %xmm9, %xmm9
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm8 = xmm8[0,1],xmm9[0],xmm8[3]
|
|
; NOFMA-NEXT: vaddss %xmm5, %xmm1, %xmm9
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm10 = xmm1[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm11 = xmm5[1,0]
|
|
; NOFMA-NEXT: vaddss %xmm11, %xmm10, %xmm10
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm1, %xmm11
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm12 = xmm11[1,0]
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm5, %xmm13
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm14 = xmm13[1,0]
|
|
; NOFMA-NEXT: vaddss %xmm14, %xmm12, %xmm12
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm14 = xmm0[1,1,3,3]
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm15 = xmm4[1,1,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm15, %xmm14, %xmm14
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm14[0],xmm2[2,3]
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm3 = xmm4[3,3,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm3, %xmm0, %xmm0
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm2 = xmm6[3,3,3,3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm3 = xmm7[3,3,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm3, %xmm2, %xmm2
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm2 = xmm8[0,1,2],xmm2[0]
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm4 = xmm5[1,1,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm4, %xmm3, %xmm3
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm3 = xmm9[0],xmm3[0],xmm9[2,3]
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm10[0],xmm3[3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm1 = xmm1[3,3,3,3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm4 = xmm5[3,3,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm4, %xmm1, %xmm1
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0]
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm3 = xmm11[1,1,3,3]
|
|
; NOFMA-NEXT: vmovshdup {{.*#+}} xmm4 = xmm13[1,1,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm4, %xmm3, %xmm3
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm3 = xmm3[0,0],xmm12[0,0]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm4 = xmm11[3,3,3,3]
|
|
; NOFMA-NEXT: vshufps {{.*#+}} xmm5 = xmm13[3,3,3,3]
|
|
; NOFMA-NEXT: vsubss %xmm5, %xmm4, %xmm4
|
|
; NOFMA-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
|
|
; NOFMA-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
|
|
; NOFMA-NEXT: retq
|
|
;
|
|
; FMA3_256-LABEL: buildvector_mul_subadd_ps512:
|
|
; FMA3_256: # %bb.0: # %bb
|
|
; FMA3_256-NEXT: vfmsubadd213ps {{.*#+}} ymm0 = (ymm2 * ymm0) -/+ ymm4
|
|
; FMA3_256-NEXT: vfmsubadd213ps {{.*#+}} ymm1 = (ymm3 * ymm1) -/+ ymm5
|
|
; FMA3_256-NEXT: retq
|
|
;
|
|
; FMA3_512-LABEL: buildvector_mul_subadd_ps512:
|
|
; FMA3_512: # %bb.0: # %bb
|
|
; FMA3_512-NEXT: vfmsubadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) -/+ zmm2
|
|
; FMA3_512-NEXT: retq
|
|
;
|
|
; FMA4-LABEL: buildvector_mul_subadd_ps512:
|
|
; FMA4: # %bb.0: # %bb
|
|
; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm0 = (ymm0 * ymm2) -/+ ymm4
|
|
; FMA4-NEXT: vfmsubaddps {{.*#+}} ymm1 = (ymm1 * ymm3) -/+ ymm5
|
|
; FMA4-NEXT: retq
|
|
bb:
|
|
%A = fmul contract <16 x float> %C, %D
|
|
%A0 = extractelement <16 x float> %A, i32 0
|
|
%B0 = extractelement <16 x float> %B, i32 0
|
|
%sub0 = fadd contract float %A0, %B0
|
|
%A2 = extractelement <16 x float> %A, i32 2
|
|
%B2 = extractelement <16 x float> %B, i32 2
|
|
%sub2 = fadd contract float %A2, %B2
|
|
%A4 = extractelement <16 x float> %A, i32 4
|
|
%B4 = extractelement <16 x float> %B, i32 4
|
|
%sub4 = fadd contract float %A4, %B4
|
|
%A6 = extractelement <16 x float> %A, i32 6
|
|
%B6 = extractelement <16 x float> %B, i32 6
|
|
%sub6 = fadd contract float %A6, %B6
|
|
%A8 = extractelement <16 x float> %A, i32 8
|
|
%B8 = extractelement <16 x float> %B, i32 8
|
|
%sub8 = fadd contract float %A8, %B8
|
|
%A10 = extractelement <16 x float> %A, i32 10
|
|
%B10 = extractelement <16 x float> %B, i32 10
|
|
%sub10 = fadd contract float %A10, %B10
|
|
%A12 = extractelement <16 x float> %A, i32 12
|
|
%B12 = extractelement <16 x float> %B, i32 12
|
|
%sub12 = fadd contract float %A12, %B12
|
|
%A14 = extractelement <16 x float> %A, i32 14
|
|
%B14 = extractelement <16 x float> %B, i32 14
|
|
%sub14 = fadd contract float %A14, %B14
|
|
%A1 = extractelement <16 x float> %A, i32 1
|
|
%B1 = extractelement <16 x float> %B, i32 1
|
|
%add1 = fsub contract float %A1, %B1
|
|
%A3 = extractelement <16 x float> %A, i32 3
|
|
%B3 = extractelement <16 x float> %B, i32 3
|
|
%add3 = fsub contract float %A3, %B3
|
|
%A5 = extractelement <16 x float> %A, i32 5
|
|
%B5 = extractelement <16 x float> %B, i32 5
|
|
%add5 = fsub contract float %A5, %B5
|
|
%A7 = extractelement <16 x float> %A, i32 7
|
|
%B7 = extractelement <16 x float> %B, i32 7
|
|
%add7 = fsub contract float %A7, %B7
|
|
%A9 = extractelement <16 x float> %A, i32 9
|
|
%B9 = extractelement <16 x float> %B, i32 9
|
|
%add9 = fsub contract float %A9, %B9
|
|
%A11 = extractelement <16 x float> %A, i32 11
|
|
%B11 = extractelement <16 x float> %B, i32 11
|
|
%add11 = fsub contract float %A11, %B11
|
|
%A13 = extractelement <16 x float> %A, i32 13
|
|
%B13 = extractelement <16 x float> %B, i32 13
|
|
%add13 = fsub contract float %A13, %B13
|
|
%A15 = extractelement <16 x float> %A, i32 15
|
|
%B15 = extractelement <16 x float> %B, i32 15
|
|
%add15 = fsub contract float %A15, %B15
|
|
%vecinsert1 = insertelement <16 x float> undef, float %sub0, i32 0
|
|
%vecinsert2 = insertelement <16 x float> %vecinsert1, float %add1, i32 1
|
|
%vecinsert3 = insertelement <16 x float> %vecinsert2, float %sub2, i32 2
|
|
%vecinsert4 = insertelement <16 x float> %vecinsert3, float %add3, i32 3
|
|
%vecinsert5 = insertelement <16 x float> %vecinsert4, float %sub4, i32 4
|
|
; element 5 is undef
|
|
%vecinsert7 = insertelement <16 x float> %vecinsert5, float %sub6, i32 6
|
|
%vecinsert8 = insertelement <16 x float> %vecinsert7, float %add7, i32 7
|
|
%vecinsert9 = insertelement <16 x float> %vecinsert8, float %sub8, i32 8
|
|
%vecinsert10 = insertelement <16 x float> %vecinsert9, float %add9, i32 9
|
|
%vecinsert11 = insertelement <16 x float> %vecinsert10, float %sub10, i32 10
|
|
%vecinsert12 = insertelement <16 x float> %vecinsert11, float %add11, i32 11
|
|
; element 12 is undef
|
|
%vecinsert14 = insertelement <16 x float> %vecinsert12, float %add13, i32 13
|
|
%vecinsert15 = insertelement <16 x float> %vecinsert14, float %sub14, i32 14
|
|
%vecinsert16 = insertelement <16 x float> %vecinsert15, float %add15, i32 15
|
|
ret <16 x float> %vecinsert16
|
|
}
|
|
|
|
define <8 x double> @buildvector_mul_subadd_pd512(<8 x double> %C, <8 x double> %D, <8 x double> %B) {
|
|
; NOFMA-LABEL: buildvector_mul_subadd_pd512:
|
|
; NOFMA: # %bb.0: # %bb
|
|
; NOFMA-NEXT: vmulpd %ymm3, %ymm1, %ymm1
|
|
; NOFMA-NEXT: vmulpd %ymm2, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vaddsd %xmm4, %xmm0, %xmm2
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm0, %xmm3
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm4, %xmm6
|
|
; NOFMA-NEXT: vaddsd %xmm6, %xmm3, %xmm7
|
|
; NOFMA-NEXT: vaddsd %xmm5, %xmm1, %xmm8
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm1, %xmm1
|
|
; NOFMA-NEXT: vextractf128 $1, %ymm5, %xmm5
|
|
; NOFMA-NEXT: vaddsd %xmm5, %xmm1, %xmm9
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm4 = xmm4[1,0]
|
|
; NOFMA-NEXT: vsubsd %xmm4, %xmm0, %xmm0
|
|
; NOFMA-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm2[0],xmm0[0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm2 = xmm3[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm3 = xmm6[1,0]
|
|
; NOFMA-NEXT: vsubsd %xmm3, %xmm2, %xmm2
|
|
; NOFMA-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm7[0],xmm2[0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1,0]
|
|
; NOFMA-NEXT: vshufpd {{.*#+}} xmm3 = xmm5[1,0]
|
|
; NOFMA-NEXT: vsubsd %xmm3, %xmm1, %xmm1
|
|
; NOFMA-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm9[0],xmm1[0]
|
|
; NOFMA-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
|
; NOFMA-NEXT: vinsertf128 $1, %xmm1, %ymm8, %ymm1
|
|
; NOFMA-NEXT: retq
|
|
;
|
|
; FMA3_256-LABEL: buildvector_mul_subadd_pd512:
|
|
; FMA3_256: # %bb.0: # %bb
|
|
; FMA3_256-NEXT: vfmsubadd213pd {{.*#+}} ymm0 = (ymm2 * ymm0) -/+ ymm4
|
|
; FMA3_256-NEXT: vfmsubadd213pd {{.*#+}} ymm1 = (ymm3 * ymm1) -/+ ymm5
|
|
; FMA3_256-NEXT: retq
|
|
;
|
|
; FMA3_512-LABEL: buildvector_mul_subadd_pd512:
|
|
; FMA3_512: # %bb.0: # %bb
|
|
; FMA3_512-NEXT: vfmsubadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) -/+ zmm2
|
|
; FMA3_512-NEXT: retq
|
|
;
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; FMA4-LABEL: buildvector_mul_subadd_pd512:
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; FMA4: # %bb.0: # %bb
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; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm0 = (ymm0 * ymm2) -/+ ymm4
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; FMA4-NEXT: vfmsubaddpd {{.*#+}} ymm1 = (ymm1 * ymm3) -/+ ymm5
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; FMA4-NEXT: retq
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bb:
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%A = fmul contract <8 x double> %C, %D
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%A0 = extractelement <8 x double> %A, i32 0
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%B0 = extractelement <8 x double> %B, i32 0
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%sub0 = fadd contract double %A0, %B0
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|
%A2 = extractelement <8 x double> %A, i32 2
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|
%B2 = extractelement <8 x double> %B, i32 2
|
|
%sub2 = fadd contract double %A2, %B2
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|
%A4 = extractelement <8 x double> %A, i32 4
|
|
%B4 = extractelement <8 x double> %B, i32 4
|
|
%sub4 = fadd contract double %A4, %B4
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|
%A6 = extractelement <8 x double> %A, i32 6
|
|
%B6 = extractelement <8 x double> %B, i32 6
|
|
%sub6 = fadd contract double %A6, %B6
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|
%A1 = extractelement <8 x double> %A, i32 1
|
|
%B1 = extractelement <8 x double> %B, i32 1
|
|
%add1 = fsub contract double %A1, %B1
|
|
%A3 = extractelement <8 x double> %A, i32 3
|
|
%B3 = extractelement <8 x double> %B, i32 3
|
|
%add3 = fsub contract double %A3, %B3
|
|
%A7 = extractelement <8 x double> %A, i32 7
|
|
%B7 = extractelement <8 x double> %B, i32 7
|
|
%add7 = fsub contract double %A7, %B7
|
|
%vecinsert1 = insertelement <8 x double> undef, double %sub0, i32 0
|
|
%vecinsert2 = insertelement <8 x double> %vecinsert1, double %add1, i32 1
|
|
%vecinsert3 = insertelement <8 x double> %vecinsert2, double %sub2, i32 2
|
|
%vecinsert4 = insertelement <8 x double> %vecinsert3, double %add3, i32 3
|
|
%vecinsert5 = insertelement <8 x double> %vecinsert4, double %sub4, i32 4
|
|
; element 5 is undef
|
|
%vecinsert7 = insertelement <8 x double> %vecinsert5, double %sub6, i32 6
|
|
%vecinsert8 = insertelement <8 x double> %vecinsert7, double %add7, i32 7
|
|
ret <8 x double> %vecinsert8
|
|
}
|