derek.holloway
7502bf64a4
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55 lines
1.9 KiB
LLVM
55 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2,sse-unaligned-mem | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
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; Although we have the ability to fold an unaligned load with AVX
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; and under special conditions with some SSE implementations, we
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; can not fold the load under any circumstances in these test
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; cases because they are not 16-byte loads. The load must be
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; executed as a scalar ('movs*') with a zero extension to
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; 128-bits and then used in the packed logical ('andp*') op.
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; PR22371 - http://llvm.org/bugs/show_bug.cgi?id=22371
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define double @load_double_no_fold(double %x, double %y) {
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; SSE2-LABEL: load_double_no_fold:
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; SSE2: # %bb.0:
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; SSE2-NEXT: cmplesd %xmm0, %xmm1
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; SSE2-NEXT: movsd {{.*#+}} xmm0 = [1.0E+0,0.0E+0]
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; SSE2-NEXT: andpd %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: load_double_no_fold:
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; AVX: # %bb.0:
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; AVX-NEXT: vcmplesd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [1.0E+0,0.0E+0]
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; AVX-NEXT: vandpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cmp = fcmp oge double %x, %y
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%zext = zext i1 %cmp to i32
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%conv = sitofp i32 %zext to double
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ret double %conv
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}
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define float @load_float_no_fold(float %x, float %y) {
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; SSE2-LABEL: load_float_no_fold:
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; SSE2: # %bb.0:
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; SSE2-NEXT: cmpless %xmm0, %xmm1
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; SSE2-NEXT: movss {{.*#+}} xmm0 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
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; SSE2-NEXT: andps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: load_float_no_fold:
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; AVX: # %bb.0:
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; AVX-NEXT: vcmpless %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vmovss {{.*#+}} xmm1 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cmp = fcmp oge float %x, %y
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%zext = zext i1 %cmp to i32
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%conv = sitofp i32 %zext to float
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ret float %conv
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}
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