derek.holloway
7502bf64a4
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32 lines
1.4 KiB
LLVM
32 lines
1.4 KiB
LLVM
; RUN: not llc -mtriple=x86_64-unknown-unknown -relocation-model=pic %s -o /dev/null 2>&1 | FileCheck %s
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; Tests come from "clang/test/CodeGen/ms-inline-asm-variables.c"
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;
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; int gVar;
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; void t1() {
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; __asm add ecx, dword ptr gVar[4590 + rax + rcx*4]
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; __asm add dword ptr [gVar + rax + 45 + 23 - 53 + 60 - 2 + rcx*8], ecx
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; __asm add 1 + 1 + 2 + 3[gVar + rcx + rbx], eax
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; gVar = 3;
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; }
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@gVar = global i32 0, align 4
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; Function Attrs: noinline nounwind optnone uwtable
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define void @t1() #0 {
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; CHECK: error: Don't use 2 or more regs for mem offset in PIC model
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; CHECK: error: Don't use 2 or more regs for mem offset in PIC model
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; CHECK: error: Don't use 2 or more regs for mem offset in PIC model
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entry:
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call void asm sideeffect inteldialect "add ecx, dword ptr ${2:P}[rax + rcx * $$4 + $$4590]\0A\09add dword ptr ${0:P}[rcx + rcx * $$8 + $$73], ecx\0A\09add ${1:P}[rcx + rbx + $$7], eax", "=*m,=*m,*m,~{ecx},~{flags},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar, ptr elementtype(i32) @gVar)
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store i32 3, ptr @gVar, align 4
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ret void
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}
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attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
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attributes #1 = { nounwind }
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"wchar_size", i32 4}
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