derek.holloway
7502bf64a4
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273 lines
10 KiB
LLVM
273 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=CHECK,SSE,SSE-SLOW
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3,fast-hops | FileCheck %s --check-prefixes=CHECK,SSE,SSE-FAST
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1,AVX1-SLOW
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx,fast-hops | FileCheck %s --check-prefixes=CHECK,AVX,AVX1,AVX1-FAST
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2,fast-hops | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512vl,fast-hops | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
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; Verify that we correctly fold horizontal binop even in the presence of UNDEFs.
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define <8 x i32> @test14_undef(<8 x i32> %a, <8 x i32> %b) {
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; SSE-LABEL: test14_undef:
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; SSE: # %bb.0:
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; SSE-NEXT: phaddd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test14_undef:
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; AVX: # %bb.0:
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; AVX-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%vecext = extractelement <8 x i32> %a, i32 0
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%vecext1 = extractelement <8 x i32> %a, i32 1
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%add = add i32 %vecext, %vecext1
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%vecinit = insertelement <8 x i32> undef, i32 %add, i32 0
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%vecext2 = extractelement <8 x i32> %b, i32 2
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%vecext3 = extractelement <8 x i32> %b, i32 3
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%add4 = add i32 %vecext2, %vecext3
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%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 3
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ret <8 x i32> %vecinit5
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}
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; integer horizontal adds instead of two scalar adds followed by vector inserts.
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define <8 x i32> @test15_undef(<8 x i32> %a, <8 x i32> %b) {
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; SSE-SLOW-LABEL: test15_undef:
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; SSE-SLOW: # %bb.0:
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; SSE-SLOW-NEXT: movd %xmm0, %eax
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; SSE-SLOW-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
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; SSE-SLOW-NEXT: movd %xmm0, %ecx
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; SSE-SLOW-NEXT: addl %eax, %ecx
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; SSE-SLOW-NEXT: movd %xmm3, %eax
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; SSE-SLOW-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,1,1]
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; SSE-SLOW-NEXT: movd %xmm0, %edx
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; SSE-SLOW-NEXT: addl %eax, %edx
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; SSE-SLOW-NEXT: movd %ecx, %xmm0
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; SSE-SLOW-NEXT: movd %edx, %xmm1
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; SSE-SLOW-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
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; SSE-SLOW-NEXT: retq
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;
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; SSE-FAST-LABEL: test15_undef:
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; SSE-FAST: # %bb.0:
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; SSE-FAST-NEXT: movdqa %xmm3, %xmm1
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; SSE-FAST-NEXT: phaddd %xmm0, %xmm0
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; SSE-FAST-NEXT: phaddd %xmm3, %xmm1
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; SSE-FAST-NEXT: retq
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;
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; AVX1-SLOW-LABEL: test15_undef:
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; AVX1-SLOW: # %bb.0:
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; AVX1-SLOW-NEXT: vmovd %xmm0, %eax
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; AVX1-SLOW-NEXT: vpextrd $1, %xmm0, %ecx
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; AVX1-SLOW-NEXT: addl %eax, %ecx
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; AVX1-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm0
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; AVX1-SLOW-NEXT: vmovd %xmm0, %eax
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; AVX1-SLOW-NEXT: vpextrd $1, %xmm0, %edx
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; AVX1-SLOW-NEXT: addl %eax, %edx
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; AVX1-SLOW-NEXT: vmovd %ecx, %xmm0
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; AVX1-SLOW-NEXT: vmovd %edx, %xmm1
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; AVX1-SLOW-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
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; AVX1-SLOW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-SLOW-NEXT: retq
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;
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; AVX1-FAST-LABEL: test15_undef:
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; AVX1-FAST: # %bb.0:
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; AVX1-FAST-NEXT: vphaddd %xmm0, %xmm0, %xmm0
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; AVX1-FAST-NEXT: vextractf128 $1, %ymm1, %xmm1
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; AVX1-FAST-NEXT: vphaddd %xmm1, %xmm1, %xmm1
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; AVX1-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-FAST-NEXT: retq
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;
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; AVX2-LABEL: test15_undef:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vphaddd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test15_undef:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vphaddd %ymm1, %ymm0, %ymm0
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; AVX512-NEXT: retq
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%vecext = extractelement <8 x i32> %a, i32 0
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%vecext1 = extractelement <8 x i32> %a, i32 1
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%add = add i32 %vecext, %vecext1
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%vecinit = insertelement <8 x i32> undef, i32 %add, i32 0
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%vecext2 = extractelement <8 x i32> %b, i32 4
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%vecext3 = extractelement <8 x i32> %b, i32 5
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%add4 = add i32 %vecext2, %vecext3
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%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 6
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ret <8 x i32> %vecinit5
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}
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define <8 x i32> @PR40243_alt(<8 x i32> %a, <8 x i32> %b) {
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; SSE-LABEL: PR40243_alt:
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; SSE: # %bb.0:
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; SSE-NEXT: phaddd %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: PR40243_alt:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: PR40243_alt:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vphaddd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: PR40243_alt:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vphaddd %ymm1, %ymm0, %ymm0
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; AVX512-NEXT: retq
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%a4 = extractelement <8 x i32> %a, i32 4
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%a5 = extractelement <8 x i32> %a, i32 5
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%add4 = add i32 %a4, %a5
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%b6 = extractelement <8 x i32> %b, i32 6
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%b7 = extractelement <8 x i32> %b, i32 7
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%add7 = add i32 %b6, %b7
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%r4 = insertelement <8 x i32> undef, i32 %add4, i32 4
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%r = insertelement <8 x i32> %r4, i32 %add7, i32 7
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ret <8 x i32> %r
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}
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define <8 x i32> @test16_undef(<8 x i32> %a, <8 x i32> %b) {
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; SSE-LABEL: test16_undef:
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; SSE: # %bb.0:
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; SSE-NEXT: phaddd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test16_undef:
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; AVX: # %bb.0:
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; AVX-NEXT: vphaddd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%vecext = extractelement <8 x i32> %a, i32 0
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%vecext1 = extractelement <8 x i32> %a, i32 1
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%add = add i32 %vecext, %vecext1
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%vecinit = insertelement <8 x i32> undef, i32 %add, i32 0
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%vecext2 = extractelement <8 x i32> %a, i32 2
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%vecext3 = extractelement <8 x i32> %a, i32 3
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%add4 = add i32 %vecext2, %vecext3
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%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 1
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ret <8 x i32> %vecinit5
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}
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define <16 x i32> @test16_v16i32_undef(<16 x i32> %a, <16 x i32> %b) {
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; SSE-LABEL: test16_v16i32_undef:
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; SSE: # %bb.0:
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; SSE-NEXT: phaddd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test16_v16i32_undef:
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; AVX: # %bb.0:
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; AVX-NEXT: vphaddd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%vecext = extractelement <16 x i32> %a, i32 0
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%vecext1 = extractelement <16 x i32> %a, i32 1
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%add = add i32 %vecext, %vecext1
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%vecinit = insertelement <16 x i32> undef, i32 %add, i32 0
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%vecext2 = extractelement <16 x i32> %a, i32 2
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%vecext3 = extractelement <16 x i32> %a, i32 3
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%add4 = add i32 %vecext2, %vecext3
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%vecinit5 = insertelement <16 x i32> %vecinit, i32 %add4, i32 1
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ret <16 x i32> %vecinit5
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}
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define <8 x i32> @test17_undef(<8 x i32> %a, <8 x i32> %b) {
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; SSE-LABEL: test17_undef:
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; SSE: # %bb.0:
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; SSE-NEXT: phaddd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test17_undef:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test17_undef:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test17_undef:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%vecext = extractelement <8 x i32> %a, i32 0
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%vecext1 = extractelement <8 x i32> %a, i32 1
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%add1 = add i32 %vecext, %vecext1
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%vecinit1 = insertelement <8 x i32> undef, i32 %add1, i32 0
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%vecext2 = extractelement <8 x i32> %a, i32 2
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%vecext3 = extractelement <8 x i32> %a, i32 3
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%add2 = add i32 %vecext2, %vecext3
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%vecinit2 = insertelement <8 x i32> %vecinit1, i32 %add2, i32 1
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%vecext4 = extractelement <8 x i32> %a, i32 4
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%vecext5 = extractelement <8 x i32> %a, i32 5
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%add3 = add i32 %vecext4, %vecext5
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%vecinit3 = insertelement <8 x i32> %vecinit2, i32 %add3, i32 2
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%vecext6 = extractelement <8 x i32> %a, i32 6
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%vecext7 = extractelement <8 x i32> %a, i32 7
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%add4 = add i32 %vecext6, %vecext7
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%vecinit4 = insertelement <8 x i32> %vecinit3, i32 %add4, i32 3
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ret <8 x i32> %vecinit4
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}
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define <16 x i32> @test17_v16i32_undef(<16 x i32> %a, <16 x i32> %b) {
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; SSE-LABEL: test17_v16i32_undef:
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; SSE: # %bb.0:
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; SSE-NEXT: phaddd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test17_v16i32_undef:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test17_v16i32_undef:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test17_v16i32_undef:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512-NEXT: vphaddd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%vecext = extractelement <16 x i32> %a, i32 0
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%vecext1 = extractelement <16 x i32> %a, i32 1
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%add1 = add i32 %vecext, %vecext1
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%vecinit1 = insertelement <16 x i32> undef, i32 %add1, i32 0
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%vecext2 = extractelement <16 x i32> %a, i32 2
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%vecext3 = extractelement <16 x i32> %a, i32 3
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%add2 = add i32 %vecext2, %vecext3
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%vecinit2 = insertelement <16 x i32> %vecinit1, i32 %add2, i32 1
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%vecext4 = extractelement <16 x i32> %a, i32 4
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%vecext5 = extractelement <16 x i32> %a, i32 5
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%add3 = add i32 %vecext4, %vecext5
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%vecinit3 = insertelement <16 x i32> %vecinit2, i32 %add3, i32 2
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%vecext6 = extractelement <16 x i32> %a, i32 6
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%vecext7 = extractelement <16 x i32> %a, i32 7
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%add4 = add i32 %vecext6, %vecext7
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%vecinit4 = insertelement <16 x i32> %vecinit3, i32 %add4, i32 3
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ret <16 x i32> %vecinit4
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}
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; PR175802 - shuffle simplifies to all undef/zero
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define <16 x i32> @PR175802() {
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; CHECK-LABEL: PR175802:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%avg = tail call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> undef, <8 x i16> undef)
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%src = bitcast <8 x i16> %avg to <4 x i32>
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%shift = shufflevector <4 x i32> %src, <4 x i32> zeroinitializer, <4 x i32> <i32 poison, i32 2, i32 poison, i32 poison>
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%add = add <4 x i32> %shift, %src
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%res = shufflevector <4 x i32> %add, <4 x i32> zeroinitializer, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
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ret <16 x i32> %res
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}
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