derek.holloway
7502bf64a4
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150 lines
4.9 KiB
LLVM
150 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
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define <4 x i3> @test1(ptr %in) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrl $3, %ecx
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; CHECK-NEXT: andl $7, %ecx
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: andl $7, %edx
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; CHECK-NEXT: vmovd %edx, %xmm0
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; CHECK-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrl $6, %ecx
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; CHECK-NEXT: andl $7, %ecx
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; CHECK-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: shrl $9, %eax
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; CHECK-NEXT: andl $7, %eax
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; CHECK-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%ret = load <4 x i3>, ptr %in, align 1
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ret <4 x i3> %ret
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}
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define <4 x i1> @test2(ptr %in) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrb %cl
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; CHECK-NEXT: andb $1, %cl
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: andb $1, %dl
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; CHECK-NEXT: vmovd %edx, %xmm0
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; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrb $2, %cl
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; CHECK-NEXT: andb $1, %cl
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; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: shrb $3, %al
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; CHECK-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%ret = load <4 x i1>, ptr %in, align 1
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ret <4 x i1> %ret
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}
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define <4 x i64> @test3(ptr %in) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: movzbl %al, %ecx
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; CHECK-NEXT: shrb %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: negl %eax
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; CHECK-NEXT: movl %ecx, %edx
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; CHECK-NEXT: andl $1, %edx
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; CHECK-NEXT: negl %edx
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; CHECK-NEXT: vmovd %edx, %xmm0
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; CHECK-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: shrb $2, %al
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: negl %eax
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; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
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; CHECK-NEXT: shrb $3, %cl
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: negl %eax
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; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
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; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1
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; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
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; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%wide.load35 = load <4 x i1>, ptr %in, align 1
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%sext = sext <4 x i1> %wide.load35 to <4 x i64>
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ret <4 x i64> %sext
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}
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define <16 x i4> @test4(ptr %in) nounwind {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrl $4, %ecx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: andl $15, %edx
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; CHECK-NEXT: vmovd %edx, %xmm0
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; CHECK-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrl $8, %ecx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $2, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrl $12, %ecx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrl $16, %ecx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrl $20, %ecx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $5, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrl $24, %ecx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $6, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: shrl $28, %ecx
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; CHECK-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movq %rax, %rcx
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; CHECK-NEXT: shrq $32, %rcx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movq %rax, %rcx
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; CHECK-NEXT: shrq $36, %rcx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movq %rax, %rcx
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; CHECK-NEXT: shrq $40, %rcx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movq %rax, %rcx
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; CHECK-NEXT: shrq $44, %rcx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movq %rax, %rcx
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; CHECK-NEXT: shrq $48, %rcx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movq %rax, %rcx
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; CHECK-NEXT: shrq $52, %rcx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: movq %rax, %rcx
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; CHECK-NEXT: shrq $56, %rcx
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; CHECK-NEXT: andl $15, %ecx
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; CHECK-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0
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; CHECK-NEXT: shrq $60, %rax
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; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%ret = load <16 x i4>, ptr %in, align 1
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ret <16 x i4> %ret
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}
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