derek.holloway
7502bf64a4
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38 lines
1.3 KiB
LLVM
38 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
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define i256 @PR173924(<8 x i256> %a0) {
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; CHECK-LABEL: PR173924:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edi
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %r8d
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edx
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %r10d
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; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %r11d
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; CHECK-NEXT: andl $1, %r11d
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; CHECK-NEXT: andl $1, %r9d
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; CHECK-NEXT: addl %r11d, %r9d
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; CHECK-NEXT: andl $1, %r10d
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; CHECK-NEXT: andl $1, %edx
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; CHECK-NEXT: addl %r10d, %edx
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; CHECK-NEXT: addl %r9d, %edx
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; CHECK-NEXT: andl $1, %r8d
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: addl %r8d, %esi
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: andl $1, %ecx
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; CHECK-NEXT: addl %edi, %ecx
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; CHECK-NEXT: addl %esi, %ecx
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; CHECK-NEXT: addl %edx, %ecx
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; CHECK-NEXT: vmovd %ecx, %xmm0
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; CHECK-NEXT: vmovdqu %ymm0, (%rax)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%m = and <8 x i256> %a0, splat (i256 1)
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%r = call i256 @llvm.vector.reduce.add.v8i256(<8 x i256> %m)
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ret i256 %r
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}
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