derek.holloway
7502bf64a4
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77 lines
3.0 KiB
LLVM
77 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=CHECK
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; This tests for a cyclic dependencies in the generated DAG.
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@c = external dso_local local_unnamed_addr global i32, align 4
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@a = external dso_local local_unnamed_addr global i32, align 4
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@b = external dso_local local_unnamed_addr global i32, align 4
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define void @foo() {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: movl $0, b(%rip)
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %edi
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %r8d
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; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl a(%rip)
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: movl c(%rip), %eax
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl %r8d
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; CHECK-NEXT: andl %edi, %eax
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; CHECK-NEXT: addl %ecx, %eax
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; CHECK-NEXT: andl %esi, %eax
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; CHECK-NEXT: movl %eax, (%rax)
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; CHECK-NEXT: retq
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entry:
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%e = alloca i32, align 4
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%e.0.e.0.24 = load volatile i32, ptr %e, align 4
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%e.0.e.0.25 = load volatile i32, ptr %e, align 4
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%e.0.e.0.26 = load volatile i32, ptr %e, align 4
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%e.0.e.0.27 = load volatile i32, ptr %e, align 4
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%e.0.e.0.28 = load volatile i32, ptr %e, align 4
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%e.0.e.0.29 = load volatile i32, ptr %e, align 4
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%e.0.e.0.30 = load volatile i32, ptr %e, align 4
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%e.0.e.0.31 = load volatile i32, ptr %e, align 4
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%e.0.e.0.32 = load volatile i32, ptr %e, align 4
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%e.0.e.0.33 = load volatile i32, ptr %e, align 4
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%e.0.e.0.34 = load volatile i32, ptr %e, align 4
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%e.0.e.0.35 = load volatile i32, ptr %e, align 4
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%e.0.e.0.36 = load volatile i32, ptr %e, align 4
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%e.0.e.0.37 = load volatile i32, ptr %e, align 4
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%e.0.e.0.39 = load volatile i32, ptr %e, align 4
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%tmp = load i32, ptr @a, align 4
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store i32 0, ptr @b, align 4
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%e.0.e.0.41 = load volatile i32, ptr %e, align 4
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%add17 = add nsw i32 %e.0.e.0.41, 0
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%e.0.e.0.42 = load volatile i32, ptr %e, align 4
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%tmp1 = load i32, ptr @c, align 4
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%e.0.e.0.43 = load volatile i32, ptr %e, align 4
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%div = sdiv i32 %tmp1, %e.0.e.0.43
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%and18 = and i32 %div, %e.0.e.0.42
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%e.0.e.0.44 = load volatile i32, ptr %e, align 4
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%div19 = sdiv i32 %e.0.e.0.44, %tmp
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%add20 = add nsw i32 %div19, %and18
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%and21 = and i32 %add20, %add17
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store volatile i32 %and21, ptr undef, align 4
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ret void
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}
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