derek.holloway
7502bf64a4
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87 lines
2.9 KiB
LLVM
87 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefixes=CHECK,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bw | FileCheck %s --check-prefixes=CHECK,AVX
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declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
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define i1 @parseHeaders(ptr %ptr) nounwind {
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; SSE2-LABEL: parseHeaders:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqu (%rdi), %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %eax
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; SSE2-NEXT: xorl $15, %eax
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; SSE2-NEXT: sete %al
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: parseHeaders:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movdqu (%rdi), %xmm0
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: sete %al
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: parseHeaders:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqu (%rdi), %xmm0
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; AVX-NEXT: vptest %xmm0, %xmm0
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%vload = load <2 x i64>, ptr %ptr, align 8
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%vreduce = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %vload)
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%vcheck = icmp eq i64 %vreduce, 0
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ret i1 %vcheck
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}
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define i1 @parseHeaders2_scalar_or(ptr %ptr) nounwind {
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; SSE2-LABEL: parseHeaders2_scalar_or:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqu (%rdi), %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %eax
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; SSE2-NEXT: xorl $15, %eax
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; SSE2-NEXT: sete %al
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: parseHeaders2_scalar_or:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movdqu (%rdi), %xmm0
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: sete %al
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: parseHeaders2_scalar_or:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqu (%rdi), %xmm0
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; AVX-NEXT: vptest %xmm0, %xmm0
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%vload = load <2 x i64>, ptr %ptr, align 8
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%v1 = extractelement <2 x i64> %vload, i32 0
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%v2 = extractelement <2 x i64> %vload, i32 1
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%vreduce = or i64 %v1, %v2
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%vcheck = icmp eq i64 %vreduce, 0
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ret i1 %vcheck
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}
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define i1 @parseHeaders2_scalar_and(ptr %ptr) nounwind {
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; CHECK-LABEL: parseHeaders2_scalar_and:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: testq %rax, 8(%rdi)
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%vload = load <2 x i64>, ptr %ptr, align 8
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%v1 = extractelement <2 x i64> %vload, i32 0
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%v2 = extractelement <2 x i64> %vload, i32 1
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%vreduce = and i64 %v1, %v2
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%vcheck = icmp eq i64 %vreduce, 0
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ret i1 %vcheck
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}
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