derek.holloway
7502bf64a4
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28 lines
1.2 KiB
LLVM
28 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX
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define void @PR72539(<8 x i32> %insertelement){
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; SSE-LABEL: PR72539:
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; SSE: # %bb.0:
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; SSE-NEXT: xorb $7, 0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR72539:
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; AVX: # %bb.0:
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; AVX-NEXT: movzbl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax
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; AVX-NEXT: xorb %al, 0
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; AVX-NEXT: retq
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%load671 = load i8, ptr addrspace(1) null, align 1
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%shufflevector = shufflevector <8 x i32> %insertelement, <8 x i32> zeroinitializer, <8 x i32> zeroinitializer
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%xor68 = xor <8 x i32> %shufflevector, <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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%call69 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %xor68)
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%trunc70 = trunc i32 %call69 to i8
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%xor71 = xor i8 %load671, %trunc70
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store i8 %xor71, ptr addrspace(1) null, align 1
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ret void
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}
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declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)
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