derek.holloway
7502bf64a4
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386 lines
10 KiB
LLVM
386 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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define i32 @and_freeze_load_i32_to_i8(ptr %p) {
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; CHECK-LABEL: and_freeze_load_i32_to_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, 255
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ret i32 %masked
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}
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define i64 @and_freeze_load_i64_to_i8(ptr %p) {
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; CHECK-LABEL: and_freeze_load_i64_to_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i64, ptr %p, align 8
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%freeze = freeze i64 %load
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%masked = and i64 %freeze, 255
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ret i64 %masked
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}
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define i64 @and_freeze_load_i64_to_i16(ptr %p) {
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; CHECK-LABEL: and_freeze_load_i64_to_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i64, ptr %p, align 8
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%freeze = freeze i64 %load
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%masked = and i64 %freeze, 65535
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ret i64 %masked
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}
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define i64 @and_freeze_load_i64_to_i32(ptr %p) {
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; CHECK-LABEL: and_freeze_load_i64_to_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i64, ptr %p, align 8
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%freeze = freeze i64 %load
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%masked = and i64 %freeze, 4294967295
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ret i64 %masked
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}
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define i8 @trunc_freeze_load_i32_to_i8(ptr %p) {
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; CHECK-LABEL: trunc_freeze_load_i32_to_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%trunc = trunc i32 %freeze to i8
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ret i8 %trunc
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}
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define i8 @trunc_freeze_load_i64_to_i8(ptr %p) {
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; CHECK-LABEL: trunc_freeze_load_i64_to_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i64, ptr %p, align 8
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%freeze = freeze i64 %load
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%trunc = trunc i64 %freeze to i8
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ret i8 %trunc
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}
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define i16 @trunc_freeze_load_i64_to_i16(ptr %p) {
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; CHECK-LABEL: trunc_freeze_load_i64_to_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i64, ptr %p, align 8
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%freeze = freeze i64 %load
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%trunc = trunc i64 %freeze to i16
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ret i16 %trunc
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}
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define i32 @sext_inreg_freeze_load_i8(ptr %p) {
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; CHECK-LABEL: sext_inreg_freeze_load_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movsbl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%shl = shl i32 %freeze, 24
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%ashr = ashr i32 %shl, 24
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ret i32 %ashr
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}
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define i32 @zext_trunc_freeze_load(ptr %p) {
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; CHECK-LABEL: zext_trunc_freeze_load:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i64, ptr %p, align 8
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%freeze = freeze i64 %load
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%trunc = trunc i64 %freeze to i8
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%zext = zext i8 %trunc to i32
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ret i32 %zext
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}
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define i32 @sext_trunc_freeze_load(ptr %p) {
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; CHECK-LABEL: sext_trunc_freeze_load:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movsbl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i64, ptr %p, align 8
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%freeze = freeze i64 %load
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%trunc = trunc i64 %freeze to i8
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%sext = sext i8 %trunc to i32
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ret i32 %sext
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}
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define i32 @and_freeze_volatile_load(ptr %p) {
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; CHECK-LABEL: and_freeze_volatile_load:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: retq
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%load = load volatile i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, 255
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ret i32 %masked
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}
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define i32 @and_freeze_invalid_mask(ptr %p) {
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; CHECK-LABEL: and_freeze_invalid_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: andl $170, %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, 170
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ret i32 %masked
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}
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define i32 @and_multiuse_freeze_extload_no_narrow(ptr %p) {
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; CHECK-LABEL: and_multiuse_freeze_extload_no_narrow:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %ecx
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: cmpl $42, %ecx
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; CHECK-NEXT: cmovel %ecx, %eax
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; CHECK-NEXT: retq
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%load = load i8, ptr %p
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%freeze = freeze i8 %load
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%zext = zext i8 %freeze to i32
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%cmp = icmp eq i8 %freeze, 42
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%sel = select i1 %cmp, i32 %zext, i32 0
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ret i32 %sel
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}
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define i32 @and_multiuse_freeze_narrowing(ptr %p, ptr %q) {
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; CHECK-LABEL: and_multiuse_freeze_narrowing:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %ecx
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: movl %ecx, (%rsi)
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; CHECK-NEXT: retq
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%load = load i32, ptr %p
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, 255
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store i32 %freeze, ptr %q
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ret i32 %masked
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}
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define i64 @and_multiuse_freeze_i64_narrowing(ptr %p, ptr %q) {
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; CHECK-LABEL: and_multiuse_freeze_i64_narrowing:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq (%rdi), %rcx
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: movq %rcx, (%rsi)
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; CHECK-NEXT: retq
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%load = load i64, ptr %p
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%freeze = freeze i64 %load
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%masked = and i64 %freeze, 255
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store i64 %freeze, ptr %q
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ret i64 %masked
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}
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define i32 @and_freeze_load_i32_to_i16(ptr %p) {
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; CHECK-LABEL: and_freeze_load_i32_to_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, 65535
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ret i32 %masked
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}
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define i8 @trunc_freeze_load_i16_to_i8(ptr %p) {
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; CHECK-LABEL: trunc_freeze_load_i16_to_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i16, ptr %p, align 2
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%freeze = freeze i16 %load
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%trunc = trunc i16 %freeze to i8
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ret i8 %trunc
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}
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define i16 @trunc_freeze_load_i32_to_i16(ptr %p) {
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; CHECK-LABEL: trunc_freeze_load_i32_to_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%trunc = trunc i32 %freeze to i16
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ret i16 %trunc
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}
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define i32 @sext_inreg_freeze_load_i16(ptr %p) {
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; CHECK-LABEL: sext_inreg_freeze_load_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movswl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%shl = shl i32 %freeze, 16
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%ashr = ashr i32 %shl, 16
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ret i32 %ashr
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}
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define i32 @and_freeze_load_shifted_mask(ptr %p) {
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; CHECK-LABEL: and_freeze_load_shifted_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl 1(%rdi), %eax
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; CHECK-NEXT: shll $8, %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, 65280
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ret i32 %masked
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}
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define i32 @and_freeze_load_unaligned(ptr %p) {
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; CHECK-LABEL: and_freeze_load_unaligned:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 1
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, 255
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ret i32 %masked
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}
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define i32 @trunc_freeze_load_store(ptr %p, ptr %q) {
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; CHECK-LABEL: trunc_freeze_load_store:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: movb %al, (%rsi)
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%load = load i16, ptr %p, align 4
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%freeze = freeze i16 %load
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%trunc = trunc i16 %freeze to i8
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store i8 %trunc, ptr %q, align 1
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ret i32 0
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}
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define i32 @and_freeze_atomic_load(ptr %p) {
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; CHECK-LABEL: and_freeze_atomic_load:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: movzbl %al, %eax
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; CHECK-NEXT: retq
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%load = load atomic i32, ptr %p seq_cst, align 4
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, 255
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ret i32 %masked
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}
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define i32 @and_freeze_non_contiguous_mask(ptr %p) {
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; CHECK-LABEL: and_freeze_non_contiguous_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: andl $170, %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, 170
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ret i32 %masked
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}
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define i32 @and_freeze_variable_mask(ptr %p, i32 %mask) {
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; CHECK-LABEL: and_freeze_variable_mask:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: andl (%rdi), %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%masked = and i32 %freeze, %mask
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ret i32 %masked
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}
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; SRL/SRA through freeze are not yet folded because the freeze peek-through
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; happens after the SRL early-return in reduceLoadWidth.
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define i32 @srl_freeze_load_i32(ptr %p) {
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; CHECK-LABEL: srl_freeze_load_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: shrl $8, %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%srl = lshr i32 %freeze, 8
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ret i32 %srl
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}
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define i32 @sra_freeze_load_i32(ptr %p) {
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; CHECK-LABEL: sra_freeze_load_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: sarl $8, %eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%sra = ashr i32 %freeze, 8
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ret i32 %sra
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}
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define i8 @trunc_srl_freeze_load(ptr %p) {
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; CHECK-LABEL: trunc_srl_freeze_load:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: shrl $8, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%load = load i32, ptr %p, align 4
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%freeze = freeze i32 %load
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%srl = lshr i32 %freeze, 8
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%trunc = trunc i32 %srl to i8
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ret i8 %trunc
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}
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define i16 @srl_freeze_load_i64_to_i16(ptr %p) {
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; CHECK-LABEL: srl_freeze_load_i64_to_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: shrl $16, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%load = load i64, ptr %p, align 8
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%freeze = freeze i64 %load
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%srl = lshr i64 %freeze, 16
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%trunc = trunc i64 %srl to i16
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ret i16 %trunc
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}
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@g6 = global i8 0
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@g1 = global i16 0
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; no incorrect sext -> zext
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define i1 @issue196590() {
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; CHECK-LABEL: issue196590:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq g6@GOTPCREL(%rip), %rax
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; CHECK-NEXT: movsbl (%rax), %eax
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; CHECK-NEXT: movzbl %al, %ecx
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; CHECK-NEXT: movq g1@GOTPCREL(%rip), %rdx
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; CHECK-NEXT: movw %cx, (%rdx)
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; CHECK-NEXT: leal (%rax,%rax), %ecx
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; CHECK-NEXT: cmpl %eax, %ecx
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; CHECK-NEXT: setg %al
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; CHECK-NEXT: retq
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%a = load i8, ptr @g6
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%zx = zext i8 %a to i16
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store i16 %zx, ptr @g1
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%sx = sext i8 %a to i32
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%b = load i8, ptr @g6
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%fr = freeze i8 %b
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%fr16 = sext i8 %fr to i16
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%add = add i16 %fr16, %fr16
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%selsx = sext i16 %add to i32
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%cmp = icmp sgt i32 %selsx, %sx
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ret i1 %cmp
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}
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