derek.holloway
7502bf64a4
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59 lines
1.8 KiB
LLVM
59 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 > /dev/null
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; Verify that DAGCombiner doesn't crash with an assertion failure in the
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; attempt to cast a ISD::UNDEF node to a ConstantSDNode.
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; During type legalization, the vector shift operation in function @test1 is
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; split into two legal shifts that work on <2 x i64> elements.
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; The first shift of the legalized sequence would be a shift by all undefs.
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; DAGCombiner will then try to simplify the vector shift and check if the
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; vector of shift counts is a splat. Make sure that llc doesn't crash
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; at that stage.
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define <4 x i64> @test1(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 1, i64 2>
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ret <4 x i64> %shl
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}
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; Also, verify that DAGCombiner doesn't crash when trying to combine shifts
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; with different combinations of undef elements in the vector shift count.
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define <4 x i64> @test2(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 2, i64 3, i64 undef, i64 undef>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test3(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 3, i64 undef>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test4(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 2, i64 undef, i64 3>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test5(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 undef, i64 undef>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test6(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 3, i64 undef>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test7(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 3>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test8(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 undef>
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ret <4 x i64> %shl
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}
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