derek.holloway
7502bf64a4
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115 lines
6.4 KiB
LLVM
115 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=x86_64-linux -stop-after=early-tailduplication < %s | FileCheck %s
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; TailDuplicator miscompile when TailBB has two PHIs and one PHI's source
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; from a non-duplicated pred is the other PHI's def.
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define fastcc void @misscompile_early_taildup(i32 %Value415, ptr %Ptr) {
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; CHECK-LABEL: name: misscompile_early_taildup
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; CHECK: bb.0.Block306:
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; CHECK-NEXT: successors: %bb.5(0x2a3677d4), %bb.1(0x2a3677d4), %bb.7(0x00000000), %bb.3(0x2a3677d4), %bb.6(0x015c9883)
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; CHECK-NEXT: liveins: $edi, $rsi
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edi
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; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
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; CHECK-NEXT: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY1]] :: (volatile store (s32) into %ir.Ptr)
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; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (volatile load (s32) from %ir.Ptr)
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[MOV32rm]], %subreg.sub_32bit
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY1]]
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; CHECK-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg :: (load (s64) from jump-table)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.Block307:
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; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI %2, %bb.4, [[COPY2]], %bb.0, %16, %bb.5, %20, %bb.2
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; CHECK-NEXT: [[PHI1:%[0-9]+]]:gr32 = PHI %1, %bb.4, [[MOV32r0_]], %bb.0, %28, %bb.5, %19, %bb.2
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; CHECK-NEXT: [[SUB32rm:%[0-9]+]]:gr32 = SUB32rm [[PHI]], [[COPY]], 1, $noreg, 0, $noreg, implicit-def $eflags :: (volatile load (s32) from %ir.Ptr)
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; CHECK-NEXT: JCC_1 %bb.4, 4, implicit $eflags
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.Block308:
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; CHECK-NEXT: successors: %bb.5(0x2a3677d4), %bb.1(0x2a3677d4), %bb.7(0x00000000), %bb.3(0x2a3677d4), %bb.6(0x015c9883)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
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; CHECK-NEXT: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[MOV32r0_1]] :: (volatile store (s32) into %ir.Ptr)
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; CHECK-NEXT: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (volatile load (s32) from %ir.Ptr)
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; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[MOV32rm1]], %subreg.sub_32bit
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY [[PHI]]
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY [[MOV32r0_1]]
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; CHECK-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.0, $noreg :: (load (s64) from jump-table)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.Block311:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI2:%[0-9]+]]:gr32 = PHI %2, %bb.4, [[COPY2]], %bb.0, %16, %bb.5, [[COPY4]], %bb.2
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; CHECK-NEXT: [[INC32r:%[0-9]+]]:gr32 = INC32r [[PHI2]], implicit-def dead $eflags
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr32 = COPY [[PHI2]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4..backedge:
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; CHECK-NEXT: successors: %bb.5(0x2a3677d4), %bb.1(0x2a3677d4), %bb.7(0x00000000), %bb.3(0x2a3677d4), %bb.6(0x015c9883)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI3:%[0-9]+]]:gr32 = PHI [[COPY5]], %bb.3, [[PHI]], %bb.1
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; CHECK-NEXT: [[PHI4:%[0-9]+]]:gr32 = PHI [[INC32r]], %bb.3, [[PHI1]], %bb.1
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; CHECK-NEXT: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[PHI4]] :: (volatile store (s32) into %ir.Ptr)
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; CHECK-NEXT: [[MOV32rm2:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (volatile load (s32) from %ir.Ptr)
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; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[MOV32rm2]], %subreg.sub_32bit
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; CHECK-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.0, $noreg :: (load (s64) from jump-table)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5.Block312:
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; CHECK-NEXT: successors: %bb.5(0x2a3677d4), %bb.1(0x2a3677d4), %bb.7(0x00000000), %bb.3(0x2a3677d4), %bb.6(0x015c9883)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI5:%[0-9]+]]:gr32 = PHI [[PHI4]], %bb.4, [[COPY2]], %bb.0, %16, %bb.5, [[COPY4]], %bb.2
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; CHECK-NEXT: [[MOV32rm3:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (volatile load (s32) from %ir.Ptr)
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; CHECK-NEXT: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[MOV32rm3]] :: (volatile store (s32) into %ir.Ptr)
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; CHECK-NEXT: [[MOV32rm4:%[0-9]+]]:gr32 = MOV32rm [[COPY]], 1, $noreg, 0, $noreg :: (volatile load (s32) from %ir.Ptr)
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; CHECK-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[MOV32rm4]], %subreg.sub_32bit
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:gr32 = COPY [[MOV32rm3]]
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; CHECK-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.0, $noreg :: (load (s64) from jump-table)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.6.Block313:
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; CHECK-NEXT: RET 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.7.Block319:
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Block306:
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br label %.backedge
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Block307: ; preds = %.backedge
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%Value2 = load volatile i32, ptr %Ptr
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%Value367 = icmp eq i32 %Value409, %Value2
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br i1 %Value367, label %.backedge.backedge, label %Block308
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Block308: ; preds = %Block307
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br label %.backedge.backedge
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Block311: ; preds = %.backedge
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%Value410 = add i32 %Value409, 1
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br label %.backedge.backedge
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.backedge: ; preds = %.backedge.backedge, %Block306
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%Value403 = phi i32 [ 0, %Block306 ], [ %Value409, %.backedge.backedge ]
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%Value409 = phi i32 [ %Value415, %Block306 ], [ %.be75, %.backedge.backedge ]
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store volatile i32 %Value409, ptr %Ptr
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%choice = load volatile i32, ptr %Ptr
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switch i32 %choice, label %Block319 [
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i32 1, label %Block307
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i32 0, label %Block312
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i32 19, label %Block313
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i32 18, label %Block311
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]
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Block312: ; preds = %.backedge
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%Val = load volatile i32, ptr %Ptr
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br label %.backedge.backedge
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Block313: ; preds = %.backedge
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ret void
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Block319: ; preds = %.backedge
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unreachable
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.backedge.backedge: ; preds = %Block312, %Block311, %Block308, %Block307
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%.be75 = phi i32 [ %Val, %Block312 ], [ %Value410, %Block311 ], [ %Value403, %Block307 ], [ 0, %Block308 ]
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br label %.backedge
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}
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