derek.holloway
7502bf64a4
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27 lines
949 B
LLVM
27 lines
949 B
LLVM
; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic -fast-isel | FileCheck %s
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; Bug 22859
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;
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; x32 pointers are 32-bits wide. x86-64 indirect branches use the full 64-bit
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; registers. Therefore, x32 CodeGen needs to zero extend indirectbr's target to
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; 64-bit.
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define i8 @test1() nounwind ssp {
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entry:
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%0 = select i1 undef, ; <ptr> [#uses=1]
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ptr blockaddress(@test1, %bb),
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ptr blockaddress(@test1, %bb6)
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indirectbr ptr %0, [label %bb, label %bb6]
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bb: ; preds = %entry
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ret i8 1
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bb6: ; preds = %entry
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ret i8 2
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}
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; CHECK-LABEL: @test1
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; We are looking for a movl ???, %r32 followed by a 64-bit jmp through the
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; same register.
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; CHECK: movl {{.*}}, %{{e|r}}[[REG:.[^d]*]]{{d?}}
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; CHECK-NEXT: jmpq *%r[[REG]]
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