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27 lines
1.2 KiB
YAML
27 lines
1.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=none %s -o - | FileCheck %s
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# During the MachineVerifier, it assumes that used registers have been defined
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# In this test case, while $v12_v13_v14_v15_v16 covers $v14_v15,
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# $v14_v15 is not a sub-register of $v14m2 even though they share the same register.
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# This corner case can be resolved by checking the register using RegUnit.
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...
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---
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name: func
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tracksRegLiveness: true
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tracksDebugUserValues: true
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body: |
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bb.0:
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liveins: $v0, $v8, $v9, $v10, $v11
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; CHECK-LABEL: name: func
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; CHECK: liveins: $v0, $v8, $v9, $v10, $v11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype
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renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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$v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype
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...
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