derek.holloway
7502bf64a4
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168 lines
9.2 KiB
TableGen
168 lines
9.2 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../../include %s | FileCheck -check-prefix=GISEL %s
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def SPECIAL : Register<"special"> { let Namespace = "MyTarget"; }
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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def Special32 : RegisterClass<"MyTarget", [i32], 32, (add SPECIAL)>;
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class I<dag OOps, dag IOps, list<dag> Pat>
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: Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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}
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// Try a nested physical register
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// GISEL: GIM_Try,
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE),
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// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
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// GISEL-NEXT: // MIs[0] src0
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] Operand 1
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// GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
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// GISEL-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
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// GISEL-NEXT: // MIs[1] Operand 0
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// GISEL-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: // MIs[1] src1
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// GISEL-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[1] Operand 2
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// GISEL-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
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// GISEL-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
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// GISEL-NEXT: // (st GPR32:{ *:[i32] }:$src0, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, SPECIAL:{ *:[i32] })) => (MULM_PHYS GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
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// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // SPECIAL
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// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULM_PHYS),
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // src0
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
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// GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
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// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
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// GISEL-NEXT: // GIR_Coverage, 0,
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// GISEL-NEXT: GIR_EraseRootFromParent_Done,
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def MULM_PHYS : I<(outs), (ins GPR32:$src0, GPR32:$src1),
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[(st GPR32:$src0, (mul GPR32:$src1, SPECIAL))]> {
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let Uses = [SPECIAL];
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}
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// Try nested physical registers and check on duplicated copies
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// GISEL: GIM_Try,
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE),
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// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
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// GISEL-NEXT: // MIs[0] src0
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] Operand 1
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// GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
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// GISEL-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
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// GISEL-NEXT: // MIs[1] Operand 0
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// GISEL-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: // MIs[1] Operand 1
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// GISEL-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[1] Operand 2
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// GISEL-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
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// GISEL-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1,
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// GISEL-NEXT: // (st GPR32:{ *:[i32] }:$src0, (mul:{ *:[i32] } R0:{ *:[i32] }, SPECIAL:{ *:[i32] })) => (MULMR0_PHYS GPR32:{ *:[i32] }:$src0)
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
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// GISEL-NEXT: GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // SPECIAL
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
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// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::R0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // R0
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// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULMR0_PHYS),
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // src0
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// GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
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// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
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// GISEL-NEXT: // GIR_Coverage, 1,
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// GISEL-NEXT: GIR_EraseRootFromParent_Done,
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def MULMR0_PHYS : I<(outs), (ins GPR32:$src0),
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[(st GPR32:$src0, (mul R0, SPECIAL))]> {
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let Uses = [R0, SPECIAL];
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}
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// Try a normal physical register use.
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// GISEL: GIM_Try,
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
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// GISEL-NEXT: // MIs[0] DstI[dst]
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] src0
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] Operand 2
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
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// GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0)
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
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// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
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// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS),
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0
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// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
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// GISEL-NEXT: // GIR_Coverage, 2,
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// GISEL-NEXT: GIR_EraseRootFromParent_Done,
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def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
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[(set GPR32:$dst, (add GPR32:$src0, SPECIAL))]> {
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let Uses = [SPECIAL];
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}
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// Try using the name of the physreg in another operand.
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// GISEL: GIM_Try,
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
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// GISEL-NEXT: // MIs[0] DstI[dst]
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] SPECIAL
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] Operand 2
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// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
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// GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL)
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
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// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
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// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS),
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
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// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // SPECIAL
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// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands,
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// GISEL-NEXT: // GIR_Coverage, 3,
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// GISEL-NEXT: GIR_EraseRootFromParent_Done,
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def MUL_PHYS : I<(outs GPR32:$dst), (ins GPR32:$SPECIAL),
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[(set GPR32:$dst, (mul GPR32:$SPECIAL, SPECIAL))]> {
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let Uses = [SPECIAL];
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}
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// Try giving the physical operand a name
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// def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
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// [(set GPR32:$dst, (add GPR32:$src0, SPECIAL:$special))]> {
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// let Uses = [SPECIAL];
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// }
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