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57 lines
3.0 KiB
TableGen
57 lines
3.0 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns \
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// RUN: -I %p/../../../include -I %p/../Common %s 2> %t | FileCheck %s
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// RUN: FileCheck -DFILE=%s -check-prefix=ERR %s < %t
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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def cc_out : OptionalDefOperand<i32, (ops GPR8), (ops (i8 zero_reg))>;
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def s_cc_out : OptionalDefOperand<i32, (ops GPR8, FPR32), (ops (i8 B0), F0)>;
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// CHECK-LABEL: // (add:{ *:[i32] } i32:{ *:[i32] }:$rs1, i32:{ *:[i32] }:$rs2) => (tst2:{ *:[i32] } i32:{ *:[i32] }:$rs1, i32:{ *:[i32] }:$rs2)
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// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::tst2),
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
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// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::B0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
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// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::F0), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs1
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rs2
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// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
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// CHECK-NEXT: // GIR_Coverage, 1,
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// CHECK-NEXT: GIR_EraseRootFromParent_Done,
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// CHECK-LABEL: // (imm:{ *:[i32] }):$imm => (tst1:{ *:[i32] } (imm:{ *:[i32] }):$imm)
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// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::tst1),
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
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// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
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// CHECK-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
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// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
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// CHECK-NEXT: // GIR_Coverage, 0,
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// CHECK-NEXT: GIR_EraseRootFromParent_Done,
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def tst1 : I<(outs GPR32:$rd, cc_out:$s), (ins i32imm:$imm),
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[(set GPR32:$rd, imm:$imm)]>;
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def tst2 : I<(outs GPR32:$rd, s_cc_out:$s), (ins GPR32:$rs1, GPR32:$rs2),
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[(set GPR32:$rd, (add i32:$rs1, i32:$rs2))]>;
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// TODO: There should be more tests, but any attempt to write something
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// more complex results in tablegen crashing somewhere in
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// TreePatternNode::UpdateNodeType.
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def not_leaf : OptionalDefOperand<i32, (ops GPR8), (ops (i8 imm))>;
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def not_rec : OptionalDefOperand<i32, (ops GPR8), (ops (i8 0))>;
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def not_reg : OptionalDefOperand<i32, (ops GPR8), (ops GPR8)>;
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// ERR: [[#@LINE+1]]:5: warning: Skipped pattern: optional def is not a leaf
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def tst_not_leaf : I<(outs GPR32:$rd, not_leaf:$s), (ins i32imm:$imm),
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[(set GPR32:$rd, imm:$imm)]>;
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// ERR: [[#@LINE+1]]:5: warning: Skipped pattern: optional def is not a record
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def tst_not_rec : I<(outs GPR32:$rd, not_rec:$s), (ins i32imm:$imm),
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[(set GPR32:$rd, imm:$imm)]>;
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// ERR: [[#@LINE+1]]:5: warning: Skipped pattern: optional def is not a register
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def tst_not_reg : I<(outs GPR32:$rd, not_reg:$s), (ins i32imm:$imm),
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[(set GPR32:$rd, imm:$imm)]>;
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