derek.holloway
7502bf64a4
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40 lines
1.1 KiB
TableGen
40 lines
1.1 KiB
TableGen
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo {}
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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def R0 : Register<"r0">;
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def P0 : Register<"p0">;
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def R32 : RegisterClass<"MyNS", [i32], 0, (add R0)>;
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def P1 : RegisterClass<"MyNS", [i1], 0, (add P0)>;
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def Reg3Opnd : Operand<OtherVT> {
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let MIOperandInfo = (ops R32, R32, P1);
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}
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// The following checks verify that 'MCInstrDesc' entry for 'InstA' has the
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// expected 'NumOperands' and 'NumDefs', i.e. 'InstA' should have 3 defs out of
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// 4 operands.
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// CHECK: archInstrTable {{.* = \{}}
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// CHECK: {{\{}}
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// CHECK: {{\{}} [[ID:[0-9]+]], 4, 3, 13, {{.+\}, \/\/}}
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// CHECK-SAME: InstA
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def InstA : Instruction {
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let Namespace = "MyNS";
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let Size = 13;
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// InstA should have 3 defs out of 4 operands.
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let OutOperandList = (outs Reg3Opnd:$dst);
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let InOperandList = (ins i32imm:$c);
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field bits<8> Inst;
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field bits<8> SoftFail = 0;
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let hasSideEffects = false;
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}
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defm : RemapAllTargetPseudoPointerOperands<P1>;
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