derek.holloway
7502bf64a4
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84 lines
3.5 KiB
LLVM
84 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -passes=gvn -S < %s | FileCheck %s
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%struct.t = type { ptr }
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; The loaded address and the location of the address itself are not aliased,
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; so the second reload is not necessary. Check that it can be eliminated.
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define void @test1(ptr nocapture readonly %p, i32 %v) #0 {
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; CHECK-LABEL: define void @test1(
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; CHECK-SAME: ptr readonly captures(none) [[P:%.*]], i32 [[V:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 4, !tbaa [[ANYPTR_TBAA0:![0-9]+]]
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; CHECK-NEXT: store volatile i32 [[V]], ptr [[TMP0]], align 4, !tbaa [[INT_TBAA5:![0-9]+]]
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; CHECK-NEXT: store volatile i32 [[V]], ptr [[TMP0]], align 4, !tbaa [[INT_TBAA5]]
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load ptr, ptr %p, align 4, !tbaa !1
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store volatile i32 %v, ptr %0, align 4, !tbaa !6
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%1 = load ptr, ptr %p, align 4, !tbaa !1
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store volatile i32 %v, ptr %1, align 4, !tbaa !6
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ret void
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}
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; The store via the loaded address may overwrite the address itself.
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; Make sure that both loads remain.
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define void @test2(ptr nocapture readonly %p, i32 %v) #0 {
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; CHECK-LABEL: define void @test2(
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; CHECK-SAME: ptr readonly captures(none) [[P:%.*]], i32 [[V:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P]], align 4, !tbaa [[ANYPTR_TBAA0]]
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; CHECK-NEXT: store volatile i32 [[V]], ptr [[TMP0]], align 4, !tbaa [[ANYPTR_TBAA0]]
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; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[P]], align 4, !tbaa [[ANYPTR_TBAA0]]
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; CHECK-NEXT: store volatile i32 [[V]], ptr [[TMP1]], align 4, !tbaa [[ANYPTR_TBAA0]]
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load ptr, ptr %p, align 4, !tbaa !1
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store volatile i32 %v, ptr %0, align 4, !tbaa !1
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%1 = load ptr, ptr %p, align 4, !tbaa !1
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store volatile i32 %v, ptr %1, align 4, !tbaa !1
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ret void
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}
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; The loads are ordered and non-monotonic. Although they are not aliased to
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; the stores, make sure both are preserved.
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define void @test3(ptr nocapture readonly %p, i32 %v) #0 {
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; CHECK-LABEL: define void @test3(
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; CHECK-SAME: ptr readonly captures(none) [[P:%.*]], i32 [[V:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP0:%.*]] = load atomic ptr, ptr [[P]] acquire, align 4, !tbaa [[ANYPTR_TBAA0]]
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; CHECK-NEXT: store volatile i32 [[V]], ptr [[TMP0]], align 4, !tbaa [[INT_TBAA5]]
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; CHECK-NEXT: [[TMP1:%.*]] = load atomic ptr, ptr [[P]] acquire, align 4, !tbaa [[ANYPTR_TBAA0]]
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; CHECK-NEXT: store volatile i32 [[V]], ptr [[TMP1]], align 4, !tbaa [[INT_TBAA5]]
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load atomic ptr, ptr %p acquire, align 4, !tbaa !1
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store volatile i32 %v, ptr %0, align 4, !tbaa !6
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%1 = load atomic ptr, ptr %p acquire, align 4, !tbaa !1
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store volatile i32 %v, ptr %1, align 4, !tbaa !6
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ret void
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}
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attributes #0 = { norecurse nounwind }
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!1 = !{!2, !3, i64 0}
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!2 = !{!"", !3, i64 0}
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!3 = !{!"any pointer", !4, i64 0}
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!4 = !{!"omnipotent char", !5, i64 0}
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!5 = !{!"Simple C/C++ TBAA"}
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!6 = !{!7, !7, i64 0}
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!7 = !{!"int", !4, i64 0}
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;.
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; CHECK: [[ANYPTR_TBAA0]] = !{[[META1:![0-9]+]], [[META2:![0-9]+]], i64 0}
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; CHECK: [[META1]] = !{!"", [[META2]], i64 0}
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; CHECK: [[META2]] = !{!"any pointer", [[META3:![0-9]+]], i64 0}
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; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
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; CHECK: [[META4]] = !{!"Simple C/C++ TBAA"}
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; CHECK: [[INT_TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
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; CHECK: [[META6]] = !{!"int", [[META3]], i64 0}
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;.
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