derek.holloway
7502bf64a4
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54 lines
1.8 KiB
LLVM
54 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
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; RUN: opt -S -passes=indvars < %s | FileCheck %s
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target datalayout = "n8:16:32:64"
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; The udiv should not get hoisted into the preheader (past a conditional).
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define i32 @test(i1 %c, i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: define i32 @test(
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; CHECK-SAME: i1 [[C:%.*]], i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[ADD9:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br i1 [[C]], label [[IF:%.*]], label [[LOOP_LATCH]]
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; CHECK: if:
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; CHECK-NEXT: [[UDIV:%.*]] = udiv i32 [[ARG1]], [[ARG2]]
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[UDIV]], [[PHI]]
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ADD]] to i64
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; CHECK-NEXT: br label [[LOOP2:%.*]]
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; CHECK: loop2:
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; CHECK-NEXT: [[PHI6:%.*]] = phi i64 [ [[ADD7:%.*]], [[LOOP2]] ], [ 0, [[IF]] ]
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; CHECK-NEXT: [[ADD7]] = add nuw nsw i64 [[PHI6]], 1
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; CHECK-NEXT: [[ICMP:%.*]] = icmp samesign ult i64 [[PHI6]], [[ZEXT]]
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; CHECK-NEXT: br i1 [[ICMP]], label [[LOOP2]], label [[LOOP_LATCH_LOOPEXIT:%.*]]
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; CHECK: loop.latch.loopexit:
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[ADD9]] = add i32 [[PHI]], 1
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; CHECK-NEXT: br label [[LOOP]]
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;
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entry:
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br label %loop
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loop:
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%phi = phi i32 [ %add9, %loop.latch ], [ 0, %entry ]
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br i1 %c, label %if, label %loop.latch
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if:
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%udiv = udiv i32 %arg1, %arg2
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%add = add i32 %udiv, %phi
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%zext = zext i32 %add to i64
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br label %loop2
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loop2:
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%phi6 = phi i64 [ %add7, %loop2 ], [ 0, %if ]
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%add7 = add i64 %phi6, 1
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%icmp = icmp slt i64 %phi6, %zext
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br i1 %icmp, label %loop2, label %loop.latch
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loop.latch:
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%add9 = add i32 %phi, 1
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br label %loop
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}
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