derek.holloway
7502bf64a4
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124 lines
7.1 KiB
LLVM
124 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt < %s -p instcombine -S | FileCheck %s
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define <4 x i32> @binop_splice_left(<4 x i32> %v1, <4 x i32> %v2, i32 %offset) {
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; CHECK-LABEL: define <4 x i32> @binop_splice_left(
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; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET:%.*]]) {
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; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[V2]]
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; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
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; CHECK-NEXT: ret <4 x i32> [[RES]]
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;
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%splice1 = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
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%splice2 = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v2, <4 x i32> poison, i32 %offset)
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%res = add <4 x i32> %splice1, %splice2
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ret <4 x i32> %res
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}
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define <4 x i32> @binop_splice_left_rhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
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; CHECK-LABEL: define <4 x i32> @binop_splice_left_rhs_splat(
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; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
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; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
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; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[SPLAT]]
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; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
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; CHECK-NEXT: ret <4 x i32> [[RES]]
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;
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%splice = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
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%head = insertelement <4 x i32> poison, i32 %x, i32 0
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%splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
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%res = add <4 x i32> %splice, %splat
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ret <4 x i32> %res
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}
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define <4 x i32> @binop_splice_left_lhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
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; CHECK-LABEL: define <4 x i32> @binop_splice_left_lhs_splat(
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; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
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; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
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; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[SPLAT]], [[V1]]
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; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
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; CHECK-NEXT: ret <4 x i32> [[RES]]
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;
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%splice = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
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%head = insertelement <4 x i32> poison, i32 %x, i32 0
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%splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
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%res = add <4 x i32> %splat, %splice
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ret <4 x i32> %res
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}
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define <4 x i32> @binop_splice_right(<4 x i32> %v1, <4 x i32> %v2, i32 %offset) {
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; CHECK-LABEL: define <4 x i32> @binop_splice_right(
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; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET:%.*]]) {
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; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[V2]]
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; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
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; CHECK-NEXT: ret <4 x i32> [[RES]]
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;
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%splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
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%splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> poison, i32 %offset)
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%res = add <4 x i32> %splice1, %splice2
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ret <4 x i32> %res
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}
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define <4 x i32> @binop_splice_right_rhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
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; CHECK-LABEL: define <4 x i32> @binop_splice_right_rhs_splat(
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; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
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; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
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; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[SPLAT]]
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; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
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; CHECK-NEXT: ret <4 x i32> [[RES]]
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;
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%splice = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
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%head = insertelement <4 x i32> poison, i32 %x, i32 0
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%splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
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%res = add <4 x i32> %splice, %splat
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ret <4 x i32> %res
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}
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define <4 x i32> @binop_splice_right_lhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
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; CHECK-LABEL: define <4 x i32> @binop_splice_right_lhs_splat(
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; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
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; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
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; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[SPLAT]], [[V1]]
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; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
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; CHECK-NEXT: ret <4 x i32> [[RES]]
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;
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%splice = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
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%head = insertelement <4 x i32> poison, i32 %x, i32 0
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%splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
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%res = add <4 x i32> %splat, %splice
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ret <4 x i32> %res
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}
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; Negative test, mismatched offset
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define <4 x i32> @binop_splice_mismatched_offset(<4 x i32> %v1, <4 x i32> %v2, i32 %offset1, i32 %offset2) {
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; CHECK-LABEL: define <4 x i32> @binop_splice_mismatched_offset(
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; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET1:%.*]], i32 [[OFFSET2:%.*]]) {
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; CHECK-NEXT: [[SPLICE1:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V1]], <4 x i32> poison, i32 [[OFFSET1]])
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; CHECK-NEXT: [[SPLICE2:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V2]], <4 x i32> poison, i32 [[OFFSET2]])
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; CHECK-NEXT: [[RES:%.*]] = add <4 x i32> [[SPLICE1]], [[SPLICE2]]
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; CHECK-NEXT: ret <4 x i32> [[RES]]
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;
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%splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset1)
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%splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> poison, i32 %offset2)
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%res = add <4 x i32> %splice1, %splice2
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ret <4 x i32> %res
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}
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; Negative test, non poison vector operand
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define <4 x i32> @binop_splice_mismatched_vector(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, i32 %offset) {
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; CHECK-LABEL: define <4 x i32> @binop_splice_mismatched_vector(
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; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], <4 x i32> [[V3:%.*]], i32 [[OFFSET:%.*]]) {
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; CHECK-NEXT: [[SPLICE1:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V1]], <4 x i32> [[V3]], i32 [[OFFSET]])
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; CHECK-NEXT: [[SPLICE2:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V2]], <4 x i32> [[V3]], i32 [[OFFSET]])
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; CHECK-NEXT: [[RES:%.*]] = add <4 x i32> [[SPLICE1]], [[SPLICE2]]
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; CHECK-NEXT: ret <4 x i32> [[RES]]
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;
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%splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> %v3, i32 %offset)
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%splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> %v3, i32 %offset)
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%res = add <4 x i32> %splice1, %splice2
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ret <4 x i32> %res
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}
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