derek.holloway
7502bf64a4
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206 lines
9.0 KiB
LLVM
206 lines
9.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -loop-reduce %s -S -o - | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; Tests where the loop termination condition is not generated by a compare.
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; The call to get.active.lane.mask in the loop should use the postincrement
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; value of %index.
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define void @lane_mask(ptr %dst, i64 %n) #0 {
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; CHECK-LABEL: define void @lane_mask(
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; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[VSCALEX4:%.*]] = shl i64 [[VSCALE]], 2
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; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 [[N]])
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[TMP1:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP0]]
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; CHECK-NEXT: tail call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> splat (i32 1), ptr align 4 [[SCEVGEP]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK]])
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; CHECK-NEXT: [[TMP1]] = add i64 [[IV]], [[VSCALEX4]]
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; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[TMP1]], i64 [[N]])
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; CHECK-NEXT: [[COND:%.*]] = extractelement <vscale x 4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0
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; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT:.*]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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%vscale = tail call i64 @llvm.vscale.i64()
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%vscalex4 = shl i64 %vscale, 2
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%active.lane.mask.entry = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 %n)
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%active.lane.mask = phi <vscale x 4 x i1> [ %active.lane.mask.entry, %entry ], [ %active.lane.mask.next, %loop ]
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%gep = getelementptr inbounds nuw i32, ptr %dst, i64 %iv
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tail call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> splat (i32 1), ptr %gep, i32 4, <vscale x 4 x i1> %active.lane.mask)
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%iv.next = add i64 %iv, %vscalex4
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%active.lane.mask.next = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 %iv.next, i64 %n)
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%cond = extractelement <vscale x 4 x i1> %active.lane.mask.next, i64 0
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; The store between the call and the branch shouldn't prevent the
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; postincement value from being used.
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define void @lane_mask_not_last(ptr %dst, i64 %n) #0 {
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; CHECK-LABEL: define void @lane_mask_not_last(
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; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[VSCALEX4:%.*]] = shl i64 [[VSCALE]], 2
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; CHECK-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 [[N]])
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[TMP0:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[ENTRY]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[IV]], 2
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP1]]
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; CHECK-NEXT: [[TMP0]] = add i64 [[IV]], [[VSCALEX4]]
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; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[TMP0]], i64 [[N]])
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; CHECK-NEXT: tail call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> splat (i32 1), ptr align 4 [[SCEVGEP]], <vscale x 4 x i1> [[ACTIVE_LANE_MASK]])
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; CHECK-NEXT: [[COND:%.*]] = extractelement <vscale x 4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0
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; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT:.*]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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%vscale = tail call i64 @llvm.vscale.i64()
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%vscalex4 = shl i64 %vscale, 2
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%active.lane.mask.entry = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 %n)
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%active.lane.mask = phi <vscale x 4 x i1> [ %active.lane.mask.entry, %entry ], [ %active.lane.mask.next, %loop ]
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%gep = getelementptr inbounds nuw i32, ptr %dst, i64 %iv
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%iv.next = add i64 %iv, %vscalex4
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%active.lane.mask.next = tail call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 %iv.next, i64 %n)
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tail call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> splat (i32 1), ptr %gep, i32 4, <vscale x 4 x i1> %active.lane.mask)
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%cond = extractelement <vscale x 4 x i1> %active.lane.mask.next, i64 0
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; The call to cmp_fn in the loop should use the postincrement value of %iv.
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define void @uses_cmp_fn(ptr %dst, i64 %n) {
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; CHECK-LABEL: define void @uses_cmp_fn(
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; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[LSR_IV]], 2
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; CHECK-NEXT: [[LSR_IV1:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP0]]
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; CHECK-NEXT: store i32 0, ptr [[LSR_IV1]], align 4
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = tail call i1 @cmp_fn(i64 [[LSR_IV_NEXT]])
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; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT:.*]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%gep = getelementptr inbounds nuw i32, ptr %dst, i64 %iv
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store i32 0, ptr %gep, align 4
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%iv.next = add i64 %iv, 1
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%cond = tail call i1 @cmp_fn(i64 %iv.next)
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; The store between the call and the branch shouldn't prevent the
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; postincement value from being used.
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define void @uses_cmp_fn_not_last(ptr %dst, i64 %n) {
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; CHECK-LABEL: define void @uses_cmp_fn_not_last(
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; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[LSR_IV:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IV]], 2
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; CHECK-NEXT: [[LSR_IV1:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP0]]
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; CHECK-NEXT: [[LSR_IV]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = tail call i1 @cmp_fn(i64 [[LSR_IV]])
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; CHECK-NEXT: store i32 0, ptr [[LSR_IV1]], align 4
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; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT:.*]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%gep = getelementptr inbounds nuw i32, ptr %dst, i64 %iv
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%iv.next = add i64 %iv, 1
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%cond = tail call i1 @cmp_fn(i64 %iv.next)
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store i32 0, ptr %gep, align 4
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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; cmp2 will use a preincrement induction variable as it isn't directly the loop
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; termination condition.
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; FIXME: We could potentially handle this by examining the operands of the 'and'
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; instruction.
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define void @cmp_and(ptr %dst, i64 %n) {
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; CHECK-LABEL: define void @cmp_and(
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; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[LOOP]] ], [ [[DST]], %[[ENTRY]] ]
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ [[TMP0]], %[[ENTRY]] ]
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; CHECK-NEXT: [[VAL:%.*]] = load i64, ptr [[LSR_IV1]], align 8
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i64 [[VAL]], [[N]]
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i64 [[LSR_IV]], 0
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; CHECK-NEXT: [[COND:%.*]] = and i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1
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; CHECK-NEXT: [[SCEVGEP]] = getelementptr i8, ptr [[LSR_IV1]], i64 4
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; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT:.*]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%gep = getelementptr inbounds nuw i32, ptr %dst, i64 %iv
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%val = load i64, ptr %gep, align 8
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%iv.next = add i64 %iv, 1
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%cmp1 = icmp ne i64 %val, %n
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%cmp2 = icmp ne i64 %iv.next, %n
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%cond = and i1 %cmp1, %cmp2
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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declare i64 @llvm.vscale.i64()
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declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64, i64)
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declare void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32>, ptr captures(none), i32 immarg, <vscale x 4 x i1>)
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declare i1 @cmp_fn(i64)
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attributes #0 = { "target-features"="+sve2" }
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