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TheRock/compiler/amd-llvm/llvm/test/Transforms/LoopVectorize/tail-folding-masked-mem-opts.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -p loop-vectorize -force-vector-width=2 -force-target-supports-masked-memory-ops=true -tail-folding-policy=must-fold-tail -S %s | FileCheck %s --check-prefixes=CHECK,CHECK-MASKED
; RUN: opt -p loop-vectorize -force-vector-width=2 -force-target-supports-masked-memory-ops=false -tail-folding-policy=must-fold-tail -S %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREDICATE
; Tests -force-target-supports-masked-memory-ops=false/true.
; With -force-target-supports-masked-memory-ops=true masked memory operations should be used.
define void @simple_memcpy(ptr noalias %dst, ptr noalias %src, i64 %n) {
; CHECK-MASKED-LABEL: define void @simple_memcpy(
; CHECK-MASKED-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i64 [[N:%.*]]) {
; CHECK-MASKED-NEXT: [[ENTRY:.*:]]
; CHECK-MASKED-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
; CHECK-MASKED-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK-MASKED: [[VECTOR_PH]]:
; CHECK-MASKED-NEXT: [[N_RND_UP:%.*]] = add i64 [[UMAX]], 1
; CHECK-MASKED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2
; CHECK-MASKED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
; CHECK-MASKED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[UMAX]], 1
; CHECK-MASKED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0
; CHECK-MASKED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-MASKED-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-MASKED: [[VECTOR_BODY]]:
; CHECK-MASKED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-MASKED-NEXT: [[VEC_IV:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-MASKED-NEXT: [[TMP0:%.*]] = icmp ule <2 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]]
; CHECK-MASKED-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[INDEX]]
; CHECK-MASKED-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 4 [[TMP1]], <2 x i1> [[TMP0]], <2 x i32> poison)
; CHECK-MASKED-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[DST]], i64 [[INDEX]]
; CHECK-MASKED-NEXT: call void @llvm.masked.store.v2i32.p0(<2 x i32> [[WIDE_MASKED_LOAD]], ptr align 4 [[TMP2]], <2 x i1> [[TMP0]])
; CHECK-MASKED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2
; CHECK-MASKED-NEXT: [[VEC_IND_NEXT]] = add nuw <2 x i64> [[VEC_IV]], splat (i64 2)
; CHECK-MASKED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MASKED-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-MASKED: [[MIDDLE_BLOCK]]:
; CHECK-MASKED-NEXT: br label %[[EXIT:.*]]
; CHECK-MASKED: [[EXIT]]:
; CHECK-MASKED-NEXT: ret void
;
; CHECK-PREDICATE-LABEL: define void @simple_memcpy(
; CHECK-PREDICATE-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i64 [[N:%.*]]) {
; CHECK-PREDICATE-NEXT: [[ENTRY:.*:]]
; CHECK-PREDICATE-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
; CHECK-PREDICATE-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK-PREDICATE: [[VECTOR_PH]]:
; CHECK-PREDICATE-NEXT: [[N_RND_UP:%.*]] = add i64 [[UMAX]], 1
; CHECK-PREDICATE-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2
; CHECK-PREDICATE-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
; CHECK-PREDICATE-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[UMAX]], 1
; CHECK-PREDICATE-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0
; CHECK-PREDICATE-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-PREDICATE-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-PREDICATE: [[VECTOR_BODY]]:
; CHECK-PREDICATE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE2:.*]] ]
; CHECK-PREDICATE-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE2]] ]
; CHECK-PREDICATE-NEXT: [[TMP0:%.*]] = icmp ule <2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]
; CHECK-PREDICATE-NEXT: [[TMP1:%.*]] = extractelement <2 x i1> [[TMP0]], i64 0
; CHECK-PREDICATE-NEXT: br i1 [[TMP1]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
; CHECK-PREDICATE: [[PRED_STORE_IF]]:
; CHECK-PREDICATE-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[INDEX]]
; CHECK-PREDICATE-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
; CHECK-PREDICATE-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[DST]], i64 [[INDEX]]
; CHECK-PREDICATE-NEXT: store i32 [[TMP4]], ptr [[TMP5]], align 4
; CHECK-PREDICATE-NEXT: br label %[[PRED_STORE_CONTINUE]]
; CHECK-PREDICATE: [[PRED_STORE_CONTINUE]]:
; CHECK-PREDICATE-NEXT: [[TMP6:%.*]] = extractelement <2 x i1> [[TMP0]], i64 1
; CHECK-PREDICATE-NEXT: br i1 [[TMP6]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2]]
; CHECK-PREDICATE: [[PRED_STORE_IF1]]:
; CHECK-PREDICATE-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 1
; CHECK-PREDICATE-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[TMP7]]
; CHECK-PREDICATE-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
; CHECK-PREDICATE-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP7]]
; CHECK-PREDICATE-NEXT: store i32 [[TMP9]], ptr [[TMP10]], align 4
; CHECK-PREDICATE-NEXT: br label %[[PRED_STORE_CONTINUE2]]
; CHECK-PREDICATE: [[PRED_STORE_CONTINUE2]]:
; CHECK-PREDICATE-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2
; CHECK-PREDICATE-NEXT: [[VEC_IND_NEXT]] = add nuw <2 x i64> [[VEC_IND]], splat (i64 2)
; CHECK-PREDICATE-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-PREDICATE-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-PREDICATE: [[MIDDLE_BLOCK]]:
; CHECK-PREDICATE-NEXT: br label %[[EXIT:.*]]
; CHECK-PREDICATE: [[EXIT]]:
; CHECK-PREDICATE-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]
%src.ptr = getelementptr i32, ptr %src, i64 %iv
%data = load i32, ptr %src.ptr
%dest.ptr = getelementptr i32, ptr %dst, i64 %iv
store i32 %data, ptr %dest.ptr
%iv.next = add nsw i64 %iv, 1
%not.exit = icmp ult i64 %iv.next, %n
br i1 %not.exit, label %loop, label %exit
exit:
ret void
}
; Negative test: Non-consecutive load/stores cannot be masked.
define void @non_consecutive_copy(ptr noalias %dst, ptr noalias %src, i64 %n) {
; CHECK-LABEL: define void @non_consecutive_copy(
; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[UMAX]], 1
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
; CHECK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[UMAX]], 1
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE3:.*]] ]
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE3]] ]
; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]
; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i64> [[VEC_IND]], splat (i64 1)
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i1> [[TMP0]], i64 0
; CHECK-NEXT: br i1 [[TMP2]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
; CHECK: [[PRED_STORE_IF]]:
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP1]], i64 0
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP3]]
; CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP7]], align 4
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
; CHECK: [[PRED_STORE_CONTINUE]]:
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP0]], i64 1
; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_STORE_IF2:.*]], label %[[PRED_STORE_CONTINUE3]]
; CHECK: [[PRED_STORE_IF2]]:
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP1]], i64 1
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[SRC]], i64 [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP9]]
; CHECK-NEXT: store i32 [[TMP11]], ptr [[TMP13]], align 4
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE3]]
; CHECK: [[PRED_STORE_CONTINUE3]]:
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX1]], 2
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 2)
; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: br label %[[EXIT:.*]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]
%index = mul i64 %iv, 2
%src.ptr = getelementptr i32, ptr %src, i64 %index
%data = load i32, ptr %src.ptr
%dest.ptr = getelementptr i32, ptr %dst, i64 %index
store i32 %data, ptr %dest.ptr
%iv.next = add nsw i64 %iv, 1
%not.exit = icmp ult i64 %iv.next, %n
br i1 %not.exit, label %loop, label %exit
exit:
ret void
}
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