derek.holloway
7502bf64a4
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117 lines
3.5 KiB
LLVM
117 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=newgvn < %s | FileCheck %s
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; Check that we do not use keywords only available for some members of a
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; congruence class when simplifying.
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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@f = external global i64, align 8
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@b = external global i1, align 8
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define i64 @ashr_lsh_nsw(i64 %tmp) {
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; CHECK-LABEL: @ashr_lsh_nsw(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
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; CHECK-NEXT: store i64 [[CONV3]], ptr @f, align 8
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; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
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; CHECK-NEXT: ret i64 [[CONV7]]
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;
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entry: ; preds = %if.then
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%conv3 = shl nsw i64 %tmp, 32
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store i64 %conv3, ptr @f, align 8
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%sext = shl i64 %tmp, 32
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%conv7 = ashr exact i64 %sext, 32
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ret i64 %conv7
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}
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define i64 @ashr_lsh_nuw(i64 %tmp) {
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; CHECK-LABEL: @ashr_lsh_nuw(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
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; CHECK-NEXT: store i64 [[CONV3]], ptr @f, align 8
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; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
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; CHECK-NEXT: ret i64 [[CONV7]]
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;
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entry: ; preds = %if.then
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%conv3 = shl nuw i64 %tmp, 32
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store i64 %conv3, ptr @f, align 8
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%sext = shl i64 %tmp, 32
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%conv7 = ashr exact i64 %sext, 32
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ret i64 %conv7
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}
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define i64 @lshr_lsh_nuw(i64 %tmp) {
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; CHECK-LABEL: @lshr_lsh_nuw(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
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; CHECK-NEXT: store i64 [[CONV3]], ptr @f, align 8
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; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[CONV3]], 32
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; CHECK-NEXT: ret i64 [[LSHR]]
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;
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entry:
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%conv3 = shl nuw i64 %tmp, 32
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store i64 %conv3, ptr @f, align 8
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%sext = shl i64 %tmp, 32
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%lshr = lshr i64 %sext, 32
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ret i64 %lshr
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}
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define i32 @udiv_exact_mul(i32 %x, i32 %y, i1 %arg2) {
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; CHECK-LABEL: @udiv_exact_mul(
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; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB2:%.*]], label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[S1:%.*]] = udiv exact i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[S2:%.*]] = mul i32 [[S1]], [[Y]]
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; CHECK-NEXT: ret i32 [[S2]]
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; CHECK: bb2:
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; CHECK-NEXT: [[S1_2:%.*]] = udiv i32 [[X]], [[Y]]
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; CHECK-NEXT: [[S2_2:%.*]] = mul i32 [[S1_2]], [[Y]]
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; CHECK-NEXT: ret i32 [[S2_2]]
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;
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br i1 %arg2, label %bb2, label %bb1
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bb1:
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%s1 = udiv exact i32 %x, %y
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%s2 = mul i32 %s1, %y
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ret i32 %s2
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bb2:
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%s1.2 = udiv i32 %x, %y
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%s2.2 = mul i32 %s1.2, %y
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ret i32 %s2.2
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}
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define i1 @add_nuw_icmp(i32 %x, i32 %y, i1 %arg2) {
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; CHECK-LABEL: @add_nuw_icmp(
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; CHECK-NEXT: br i1 [[ARG2:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[Z:%.*]] = add i32 [[Y:%.*]], 1
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; CHECK-NEXT: [[S1:%.*]] = add i32 [[X:%.*]], [[Z]]
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; CHECK-NEXT: [[S2:%.*]] = add i32 [[X]], [[Y]]
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[S1]], [[S2]]
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; CHECK-NEXT: ret i1 [[C]]
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; CHECK: bb2:
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; CHECK-NEXT: [[Z_2:%.*]] = add nuw i32 [[Y]], 1
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; CHECK-NEXT: [[S1_2:%.*]] = add nuw i32 [[X]], [[Z_2]]
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; CHECK-NEXT: [[S2_2:%.*]] = add nuw i32 [[X]], [[Y]]
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; CHECK-NEXT: [[C_2:%.*]] = icmp ugt i32 [[S1_2]], [[S2_2]]
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; CHECK-NEXT: ret i1 [[C_2]]
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;
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br i1 %arg2, label %bb1, label %bb2
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bb1:
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%z = add i32 %y, 1
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%s1 = add i32 %x, %z
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%s2 = add i32 %x, %y
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%c = icmp ugt i32 %s1, %s2
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ret i1 %c
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bb2:
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%z.2 = add nuw i32 %y, 1
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%s1.2 = add nuw i32 %x, %z.2
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%s2.2 = add nuw i32 %x, %y
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%c.2 = icmp ugt i32 %s1.2, %s2.2
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ret i1 %c.2
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}
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