derek.holloway
7502bf64a4
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89 lines
5.4 KiB
LLVM
89 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -passes=separate-const-offset-from-gep -S %s | FileCheck %s
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; This test is intended to test that the separate-const-offset-from-gep
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; pass will still separate offsets even if the base offset is large.
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@global_smem = external addrspace(3) global [0 x i8], align 16
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define void @large_base_offset(ptr addrspace(1) writeonly %out, i32 %idx) {
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; CHECK-LABEL: define void @large_base_offset(
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; CHECK-SAME: ptr addrspace(1) writeonly [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP2]], 10
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; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP5:%.*]] = shl nuw nsw i32 [[TMP4]], 1
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; CHECK-NEXT: [[TMP6:%.*]] = or disjoint i32 [[TMP5]], [[TMP3]]
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; CHECK-NEXT: [[TMP7:%.*]] = shl nuw nsw i32 [[TMP2]], 5
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) @global_smem, i32 67584
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; CHECK-NEXT: [[TMP9:%.*]] = or disjoint i32 [[TMP6]], 16384
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; CHECK-NEXT: [[TMP10:%.*]] = lshr exact i32 [[TMP9]], 5
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; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[TMP10]], 992
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(3) [[TMP8]], i32 [[TMP6]]
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(3) [[TMP12]], i32 [[TMP11]]
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(3) [[TMP13]], i32 16384
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; CHECK-NEXT: [[TMP15:%.*]] = load <16 x half>, ptr addrspace(3) [[TMP14]], align 32
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; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <16 x half> [[TMP15]], <16 x half> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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; CHECK-NEXT: store <8 x half> [[TMP16]], ptr addrspace(1) [[TMP0]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%idx_low_bits = and i32 %idx, 15
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%row_offset = shl nuw nsw i32 %idx_low_bits, 10
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%idx_bit4 = and i32 %idx, 16
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%idx_bit4_shifted = shl nuw nsw i32 %idx_bit4, 1
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%combined_offset = or disjoint i32 %idx_bit4_shifted, %row_offset
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%lane_offset = shl nuw nsw i32 %idx_low_bits, 5
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%lds_large_base = getelementptr i8, ptr addrspace(3) @global_smem, i32 67584
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%combined_offset_with_stride = or disjoint i32 %combined_offset, 16384
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%aligned_offset = lshr exact i32 %combined_offset_with_stride, 5
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%row_alignment = and i32 %aligned_offset, 992
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%lds_vector_ptr = getelementptr inbounds nuw i8, ptr addrspace(3) %lds_large_base, i32 %combined_offset_with_stride
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%lds_lane_ptr = getelementptr inbounds nuw i8, ptr addrspace(3) %lds_vector_ptr, i32 %row_alignment
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%lds_wide_load = load <16 x half>, ptr addrspace(3) %lds_lane_ptr, align 32
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%upper_half = shufflevector <16 x half> %lds_wide_load, <16 x half> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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store <8 x half> %upper_half, ptr addrspace(1) %out, align 16
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ret void
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}
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define void @small_base_offset(ptr addrspace(1) writeonly %out, i32 %idx) {
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; CHECK-LABEL: define void @small_base_offset(
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; CHECK-SAME: ptr addrspace(1) writeonly [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw nsw i32 [[TMP2]], 10
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; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP5:%.*]] = shl nuw nsw i32 [[TMP4]], 1
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; CHECK-NEXT: [[TMP6:%.*]] = or disjoint i32 [[TMP5]], [[TMP3]]
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; CHECK-NEXT: [[TMP7:%.*]] = shl nuw nsw i32 [[TMP2]], 5
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; CHECK-NEXT: [[TMP8:%.*]] = or disjoint i32 [[TMP6]], 16384
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; CHECK-NEXT: [[TMP9:%.*]] = lshr exact i32 [[TMP8]], 5
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; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP9]], 992
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; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr addrspace(3) @global_smem, i32 [[TMP6]]
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP11]], i32 [[TMP10]]
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP12]], i32 16388
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; CHECK-NEXT: [[TMP14:%.*]] = load <16 x half>, ptr addrspace(3) [[TMP13]], align 32
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; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <16 x half> [[TMP14]], <16 x half> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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; CHECK-NEXT: store <8 x half> [[TMP15]], ptr addrspace(1) [[TMP0]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%idx_low_bits = and i32 %idx, 15
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%row_offset = shl nuw nsw i32 %idx_low_bits, 10
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%idx_bit4 = and i32 %idx, 16
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%idx_bit4_shifted = shl nuw nsw i32 %idx_bit4, 1
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%combined_offset = or disjoint i32 %idx_bit4_shifted, %row_offset
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%lane_offset = shl nuw nsw i32 %idx_low_bits, 5
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%lds_small_base = getelementptr i8, ptr addrspace(3) @global_smem, i32 4
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%combined_offset_with_stride = or disjoint i32 %combined_offset, 16384
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%aligned_offset = lshr exact i32 %combined_offset_with_stride, 5
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%row_alignment = and i32 %aligned_offset, 992
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%lds_vector_ptr = getelementptr inbounds nuw i8, ptr addrspace(3) %lds_small_base, i32 %combined_offset_with_stride
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%lds_lane_ptr = getelementptr inbounds nuw i8, ptr addrspace(3) %lds_vector_ptr, i32 %row_alignment
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%lds_wide_load = load <16 x half>, ptr addrspace(3) %lds_lane_ptr, align 32
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%upper_half = shufflevector <16 x half> %lds_wide_load, <16 x half> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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store <8 x half> %upper_half, ptr addrspace(1) %out, align 16
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ret void
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}
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