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114 lines
2.5 KiB
ArmAsm
114 lines
2.5 KiB
ArmAsm
//Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp
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// Spec Reference: dsp32shift vmax
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x11001001;
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imm32 r1, 0x11001001;
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imm32 r2, 0x12345678;
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imm32 r3, 0x11001003;
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imm32 r4, 0x11001004;
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imm32 r5, 0x11001005;
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imm32 r6, 0x11001006;
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imm32 r7, 0x11001007;
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A0 = R2;
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R0.L = VIT_MAX( R0 ) (ASL);
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R1.L = VIT_MAX( R1 ) (ASL);
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R2.L = VIT_MAX( R2 ) (ASL);
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R3.L = VIT_MAX( R3 ) (ASL);
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R4.L = VIT_MAX( R4 ) (ASL);
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R5.L = VIT_MAX( R5 ) (ASL);
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R6.L = VIT_MAX( R6 ) (ASL);
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R7.L = VIT_MAX( R7 ) (ASL);
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CHECKREG r0, 0x11001100;
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CHECKREG r1, 0x11001100;
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CHECKREG r2, 0x12345678;
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CHECKREG r3, 0x11001100;
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CHECKREG r4, 0x11001100;
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CHECKREG r5, 0x11001100;
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CHECKREG r6, 0x11001100;
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CHECKREG r7, 0x11001100;
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imm32 r0, 0xa1001001;
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imm32 r1, 0x1b001001;
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imm32 r2, 0x11c01002;
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imm32 r3, 0x110d1003;
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imm32 r4, 0x1100e004;
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imm32 r5, 0x11001f05;
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imm32 r6, 0x11001006;
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imm32 r7, 0x11001001;
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R1.L = VIT_MAX( R0 ) (ASL);
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R2.L = VIT_MAX( R1 ) (ASL);
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R3.L = VIT_MAX( R2 ) (ASL);
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R4.L = VIT_MAX( R3 ) (ASL);
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R5.L = VIT_MAX( R4 ) (ASL);
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R6.L = VIT_MAX( R5 ) (ASL);
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R7.L = VIT_MAX( R6 ) (ASL);
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R0.L = VIT_MAX( R7 ) (ASL);
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CHECKREG r0, 0xA1001B00;
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CHECKREG r1, 0x1B001001;
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CHECKREG r2, 0x11C01B00;
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CHECKREG r3, 0x110D1B00;
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CHECKREG r4, 0x11001B00;
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CHECKREG r5, 0x11001B00;
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CHECKREG r6, 0x11001B00;
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CHECKREG r7, 0x11001B00;
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imm32 r0, 0x20000000;
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imm32 r1, 0x4300c001;
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imm32 r2, 0x4040c002;
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imm32 r3, 0x40056003;
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imm32 r4, 0x4000c704;
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imm32 r5, 0x4000c085;
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imm32 r6, 0x4000c096;
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imm32 r7, 0x4000c000;
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R0.L = VIT_MAX( R0 ) (ASR);
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R1.L = VIT_MAX( R1 ) (ASR);
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R2.L = VIT_MAX( R2 ) (ASR);
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R3.L = VIT_MAX( R3 ) (ASR);
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R4.L = VIT_MAX( R4 ) (ASR);
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R5.L = VIT_MAX( R5 ) (ASR);
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R6.L = VIT_MAX( R6 ) (ASR);
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R7.L = VIT_MAX( R7 ) (ASR);
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CHECKREG r0, 0x20002000;
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CHECKREG r1, 0x4300C001;
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CHECKREG r2, 0x4040C002;
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CHECKREG r3, 0x40056003;
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CHECKREG r4, 0x40004000;
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CHECKREG r5, 0x40004000;
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CHECKREG r6, 0x40004000;
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CHECKREG r7, 0x4000C000;
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imm32 r0, 0x10000000;
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imm32 r1, 0x4200c001;
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imm32 r2, 0x4030c002;
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imm32 r3, 0x4004c003;
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imm32 r4, 0x40005004;
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imm32 r5, 0x4000c605;
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imm32 r6, 0x4000c076;
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imm32 r7, 0x4000c008;
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R2.L = VIT_MAX( R0 ) (ASR);
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R3.L = VIT_MAX( R1 ) (ASR);
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R4.L = VIT_MAX( R2 ) (ASR);
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R5.L = VIT_MAX( R3 ) (ASR);
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R6.L = VIT_MAX( R4 ) (ASR);
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R7.L = VIT_MAX( R5 ) (ASR);
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R0.L = VIT_MAX( R6 ) (ASR);
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R1.L = VIT_MAX( R7 ) (ASR);
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CHECKREG r0, 0x10004030;
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CHECKREG r1, 0x42004000;
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CHECKREG r2, 0x40301000;
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CHECKREG r3, 0x4004C001;
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CHECKREG r4, 0x40004030;
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CHECKREG r5, 0x4000C001;
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CHECKREG r6, 0x40004030;
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CHECKREG r7, 0x40004000;
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pass
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