derek.holloway
7502bf64a4
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100 lines
1.9 KiB
ArmAsm
100 lines
1.9 KiB
ArmAsm
# Blackfin testcase for branching into the middle of a hardware loop
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# mach: bfin
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.include "testutils.inc"
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.macro test_prep lc:req
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loadsym P5, 1f;
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dmm32 LC0, \lc
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R5 = 0;
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R6 = 0;
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R7 = 0;
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.endm
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.macro test_check exp5:req, exp6:req, exp7:req, expLC:req
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1:
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imm32 R4, \exp5;
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CC = R4 == R5;
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IF !CC JUMP 2f;
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imm32 R4, \exp6;
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CC = R4 == R6;
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IF !CC JUMP 2f;
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imm32 R4, \exp7;
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CC = R4 == R7;
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IF !CC JUMP 2f;
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R3 = LC0;
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imm32 R4, \expLC;
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CC = R4 == R3;
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IF !CC JUMP 2f;
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JUMP 3f;
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2: fail
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3:
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.endm
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.macro test_rts entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req
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loadsym R1, \entry;
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RETS = R1;
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test_prep \lc
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RTS;
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test_check \exp5, \exp6, \exp7, \expLC
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.endm
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.macro test_jump entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req
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loadsym P1, \entry;
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test_prep \lc
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JUMP (P1);
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test_check \exp5, \exp6, \exp7, \expLC
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.endm
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start
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loadsym R1, hws;
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LT0 = R1;
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loadsym R1, hwe;
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LB0 = R1;
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test_rts hws, 0, 1, 1, 1, 0
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test_rts hws, 1, 1, 1, 1, 0
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test_rts hws, 2, 2, 2, 2, 0
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test_rts hws, 20, 20, 20, 20, 0
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test_rts hwm, 0, 0, 1, 1, 0
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test_rts hwm, 1, 0, 1, 1, 0
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test_rts hwm, 2, 1, 2, 2, 0
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test_rts hwm, 20, 19, 20, 20, 0
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test_rts hwe, 0, 0, 0, 1, 0
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test_rts hwe, 1, 0, 0, 1, 0
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test_rts hwe, 2, 1, 1, 2, 0
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test_rts hwe, 20, 19, 19, 20, 0
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test_rts hwp, 0, 0, 0, 0, 0
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test_rts hwp, 1, 0, 0, 0, 1
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test_rts hwp, 2, 0, 0, 0, 2
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test_jump hws, 0, 1, 1, 1, 0
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test_jump hws, 1, 1, 1, 1, 0
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test_jump hws, 2, 2, 2, 2, 0
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test_jump hws, 20, 20, 20, 20, 0
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test_jump hwm, 0, 0, 1, 1, 0
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test_jump hwm, 1, 0, 1, 1, 0
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test_jump hwm, 2, 1, 2, 2, 0
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test_jump hwm, 20, 19, 20, 20, 0
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test_jump hwe, 0, 0, 0, 1, 0
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test_jump hwe, 1, 0, 0, 1, 0
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test_jump hwe, 2, 1, 1, 2, 0
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test_jump hwe, 20, 19, 19, 20, 0
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test_jump hwp, 0, 0, 0, 0, 0
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test_jump hwp, 1, 0, 0, 0, 1
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test_jump hwp, 2, 0, 0, 0, 2
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pass
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hws: R5 += 1;
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hwm: R6 += 1;
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hwe: R7 += 1;
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hwp: JUMP (P5);
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