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346 lines
9.9 KiB
ArmAsm
346 lines
9.9 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_align/lmu_excpt_align.dsp
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// Description: LMU data alignment exceptions
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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include(selfcheck.inc)
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include(std.inc)
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include(mmrs.inc)
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CHECK_INIT(p5, 0xE0000000);
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// test address for DAG0
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// test address for DAG1
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// setup interrupt controller with exception handler address
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WR_MMR_LABEL(EVT3, handler, p0, r1);
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// Write fault addr MMR to known state
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WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6);
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//nop;nop;nop;nop;nop; // in lieu of CSYNC
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CSYNC;
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A0 = 0;
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// go to user mode. and enable exceptions
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LD32_LABEL(r0, User);
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RETI = R0;
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RTI;
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// Nops to work around ICache bug
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NOP;NOP;NOP;NOP;NOP;
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NOP;NOP;NOP;NOP;NOP;
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User:
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NOP;NOP;NOP;NOP;NOP;
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//-------------------------------------------------------
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// First do stores
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//-------------------------------------------------------
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// 16-bit alignment, DAG0
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LD32(i1, ((0x1000 + 1)));
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LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X01: W [ I1 ] = R1.L; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG0
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LD32(i1, ((0x1000 + 1)));
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LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X02: [ I1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG0
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LD32(i1, ((0x1000 + 2)));
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LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X03: [ I1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG0
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LD32(i1, ((0x1000 + 3)));
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LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X04: [ I1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 16-bit alignment, DAG1
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LD32(i1, ((0x1000 + 1)));
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LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X05: A0 = 0 || NOP || W [ I1 ] = R1.L; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X05, r0); // RETX should be value of X05 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG1
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LD32(i1, ((0x1000 + 1)));
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LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X06: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X06, r0); // RETX should be value of X06 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG1
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LD32(i1, ((0x1000 + 2)));
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LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X07: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X07, r0); // RETX should be value of X07 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG1
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LD32(i1, ((0x1000 + 3)));
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LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X08: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X08, r0); // RETX should be value of X08 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// Now repeat for Loads
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//-------------------------------------------------------
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// 16-bit alignment, DAG0
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LD32(i1, ((0x1000 + 1)));
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LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X11: R1.L = W [ I1 ]; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X11, r0); // RETX should be value of X11 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG0
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LD32(i1, ((0x1000 + 1)));
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LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X12: R1 = [ I1 ]; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X12, r0); // RETX should be value of X12 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG0
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LD32(i1, ((0x1000 + 2)));
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LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X13: R1 = [ I1 ]; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X13, r0); // RETX should be value of X13 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG0
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LD32(i1, ((0x1000 + 3)));
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LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X14: R1 = [ I1 ]; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X14, r0); // RETX should be value of X14 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 16-bit alignment, DAG1
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LD32(i1, ((0x1000 + 1)));
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LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X15: A0 = 0 || NOP || R1.L = W [ I1 ]; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X15, r0); // RETX should be value of X15 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG1
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LD32(i1, ((0x1000 + 1)));
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LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X16, r0); // RETX should be value of X16 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG1
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LD32(i1, ((0x1000 + 2)));
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LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X17: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X17, r0); // RETX should be value of X17 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// 32-bit alignment, DAG1
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LD32(i1, ((0x1000 + 3)));
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LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X18: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
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CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
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CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
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CHECKREG_SYM(r7, X18, r0); // RETX should be value of X18 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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dbg_pass;
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handler:
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R5 = SEQSTAT; // Get exception cause
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// read and check fail addr (addr_which_causes_exception)
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// should not be set for alignment exception
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RD_MMR(DCPLB_FAULT_ADDR, p0, r6);
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R7 = RETX; // get address of excepting instruction
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// align the offending address
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I1 = P2;
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RTX;
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// Nops to work around ICache bug
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NOP;NOP;NOP;NOP;NOP;
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NOP;NOP;NOP;NOP;NOP;
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.section MEM_0x1000,"aw"
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.dd 0x00000000
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.dd 0x00000000
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.dd 0x00000000
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.dd 0x00000000
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