derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
1269 lines
43 KiB
Plaintext
1269 lines
43 KiB
Plaintext
# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond
|
|
# mach: frv fr500 fr400
|
|
|
|
.include "testutils.inc"
|
|
|
|
start
|
|
|
|
.global cmqmachs
|
|
cmqmachs:
|
|
set_spr_immed 0x1b1b,cccr
|
|
|
|
; Positive operands
|
|
set_spr_immed 0,msr0
|
|
set_spr_immed 0,msr1
|
|
set_accg_immed 0,accg0
|
|
set_acc_immed 0,acc0
|
|
set_accg_immed 0,accg1
|
|
set_acc_immed 0,acc1
|
|
set_accg_immed 0,accg2
|
|
set_acc_immed 0,acc2
|
|
set_accg_immed 0,accg3
|
|
set_acc_immed 0,acc3
|
|
set_fr_iimmed 2,3,fr8 ; multiply small numbers
|
|
set_fr_iimmed 3,2,fr10
|
|
set_fr_iimmed 0,1,fr9 ; multiply by 0
|
|
set_fr_iimmed 2,0,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_immed 6,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_immed 6,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_immed 0,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_immed 0,acc3
|
|
|
|
set_fr_iimmed 2,1,fr8 ; multiply by 1
|
|
set_fr_iimmed 1,2,fr10
|
|
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
|
|
set_fr_iimmed 2,0x3fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_immed 8,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_immed 8,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_limmed 0,0x7ffe,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_limmed 0,0x7ffe,acc3
|
|
|
|
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
|
|
set_fr_iimmed 2,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x8008,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x8008,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_limmed 0x3fff,0x7fff,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_limmed 0x3fff,0x7fff,acc3
|
|
|
|
; Mixed operands
|
|
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,2,fr10
|
|
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
|
|
set_fr_iimmed 1,0xfffe,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x8002,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x8002,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_limmed 0x3fff,0x7ffd,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_limmed 0x3fff,0x7ffd,acc3
|
|
|
|
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
|
|
set_fr_iimmed 0,0xfffe,fr10
|
|
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
|
|
set_fr_iimmed 0xfffe,0x2001,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x8002,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x8002,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_limmed 0x3fff,0x3ffb,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_limmed 0x3fff,0x3ffb,acc3
|
|
|
|
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
|
|
set_fr_iimmed 0xfffe,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
|
|
set_fr_iimmed 0x8000,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x0002,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x0002,acc1
|
|
test_accg_immed 0xff,accg2
|
|
test_acc_limmed 0xffff,0xbffb,acc2
|
|
test_accg_immed 0xff,accg3
|
|
test_acc_limmed 0xffff,0xbffb,acc3
|
|
|
|
; Negative operands
|
|
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,0xfffe,fr10
|
|
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
|
|
set_fr_iimmed 0xfffe,0xffff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x0008,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x0008,acc1
|
|
test_accg_immed 0xff,accg2
|
|
test_acc_limmed 0xffff,0xbffd,acc2
|
|
test_accg_immed 0xff,accg3
|
|
test_acc_limmed 0xffff,0xbffd,acc3
|
|
|
|
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
|
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
|
|
set_fr_iimmed 0x8000,0x8000,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_immed 0x3fff0009,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_immed 0x3fff0009,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_immed 0x3fffbffd,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_immed 0x3fffbffd,acc3
|
|
|
|
set_accg_immed 0x7f,accg0 ; saturation
|
|
set_acc_immed 0xffffffff,acc0
|
|
set_accg_immed 0x7f,accg1
|
|
set_acc_immed 0xffffffff,acc1
|
|
set_accg_immed 0x7f,accg2 ; saturation
|
|
set_acc_immed 0xffffffff,acc2
|
|
set_accg_immed 0x7f,accg3
|
|
set_acc_immed 0xffffffff,acc3
|
|
set_fr_iimmed 1,1,fr8
|
|
set_fr_iimmed 1,1,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,1
|
|
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
|
|
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
|
|
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
|
|
test_accg_immed 0x7f,accg0
|
|
test_acc_limmed 0xffff,0xffff,acc0
|
|
test_accg_immed 0x7f,accg1
|
|
test_acc_limmed 0xffff,0xffff,acc1
|
|
test_accg_immed 0x7f,accg2
|
|
test_acc_limmed 0xffff,0xffff,acc2
|
|
test_accg_immed 0x7f,accg3
|
|
test_acc_limmed 0xffff,0xffff,acc3
|
|
|
|
set_accg_immed 0x80,accg0 ; saturation
|
|
set_acc_immed 0,acc0
|
|
set_accg_immed 0x80,accg1
|
|
set_acc_immed 0,acc1
|
|
set_accg_immed 0x80,accg2 ; saturation
|
|
set_acc_immed 0,acc2
|
|
set_accg_immed 0x80,accg3
|
|
set_acc_immed 0,acc3
|
|
set_fr_iimmed 0xffff,0,fr8
|
|
set_fr_iimmed 1,0xffff,fr10
|
|
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,1
|
|
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
|
|
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
|
|
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
|
|
test_accg_immed 0x80,accg0
|
|
test_acc_immed 0,acc0
|
|
test_accg_immed 0x80,accg1
|
|
test_acc_immed 0,acc1
|
|
test_accg_immed 0x80,accg2
|
|
test_acc_immed 0,acc2
|
|
test_accg_immed 0x80,accg3
|
|
test_acc_immed 0,acc3
|
|
|
|
; Positive operands
|
|
set_spr_immed 0,msr0
|
|
set_spr_immed 0,msr1
|
|
set_accg_immed 0,accg0
|
|
set_acc_immed 0,acc0
|
|
set_accg_immed 0,accg1
|
|
set_acc_immed 0,acc1
|
|
set_accg_immed 0,accg2
|
|
set_acc_immed 0,acc2
|
|
set_accg_immed 0,accg3
|
|
set_acc_immed 0,acc3
|
|
set_fr_iimmed 2,3,fr8 ; multiply small numbers
|
|
set_fr_iimmed 3,2,fr10
|
|
set_fr_iimmed 0,1,fr9 ; multiply by 0
|
|
set_fr_iimmed 2,0,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_immed 6,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_immed 6,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_immed 0,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_immed 0,acc3
|
|
|
|
set_fr_iimmed 2,1,fr8 ; multiply by 1
|
|
set_fr_iimmed 1,2,fr10
|
|
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
|
|
set_fr_iimmed 2,0x3fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_immed 8,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_immed 8,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_limmed 0,0x7ffe,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_limmed 0,0x7ffe,acc3
|
|
|
|
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
|
|
set_fr_iimmed 2,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x8008,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x8008,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_limmed 0x3fff,0x7fff,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_limmed 0x3fff,0x7fff,acc3
|
|
|
|
; Mixed operands
|
|
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,2,fr10
|
|
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
|
|
set_fr_iimmed 1,0xfffe,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x8002,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x8002,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_limmed 0x3fff,0x7ffd,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_limmed 0x3fff,0x7ffd,acc3
|
|
|
|
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
|
|
set_fr_iimmed 0,0xfffe,fr10
|
|
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
|
|
set_fr_iimmed 0xfffe,0x2001,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x8002,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x8002,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_limmed 0x3fff,0x3ffb,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_limmed 0x3fff,0x3ffb,acc3
|
|
|
|
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
|
|
set_fr_iimmed 0xfffe,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
|
|
set_fr_iimmed 0x8000,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x0002,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x0002,acc1
|
|
test_accg_immed 0xff,accg2
|
|
test_acc_limmed 0xffff,0xbffb,acc2
|
|
test_accg_immed 0xff,accg3
|
|
test_acc_limmed 0xffff,0xbffb,acc3
|
|
|
|
; Negative operands
|
|
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,0xfffe,fr10
|
|
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
|
|
set_fr_iimmed 0xfffe,0xffff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_limmed 0x0000,0x0008,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_limmed 0x0000,0x0008,acc1
|
|
test_accg_immed 0xff,accg2
|
|
test_acc_limmed 0xffff,0xbffd,acc2
|
|
test_accg_immed 0xff,accg3
|
|
test_acc_limmed 0xffff,0xbffd,acc3
|
|
|
|
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
|
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
|
|
set_fr_iimmed 0x8000,0x8000,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0,accg0
|
|
test_acc_immed 0x3fff0009,acc0
|
|
test_accg_immed 0,accg1
|
|
test_acc_immed 0x3fff0009,acc1
|
|
test_accg_immed 0,accg2
|
|
test_acc_immed 0x3fffbffd,acc2
|
|
test_accg_immed 0,accg3
|
|
test_acc_immed 0x3fffbffd,acc3
|
|
|
|
set_accg_immed 0x7f,accg0 ; saturation
|
|
set_acc_immed 0xffffffff,acc0
|
|
set_accg_immed 0x7f,accg1
|
|
set_acc_immed 0xffffffff,acc1
|
|
set_accg_immed 0x7f,accg2 ; saturation
|
|
set_acc_immed 0xffffffff,acc2
|
|
set_accg_immed 0x7f,accg3
|
|
set_acc_immed 0xffffffff,acc3
|
|
set_fr_iimmed 1,1,fr8
|
|
set_fr_iimmed 1,1,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,0
|
|
test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set
|
|
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
|
|
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
|
|
test_accg_immed 0x7f,accg0
|
|
test_acc_limmed 0xffff,0xffff,acc0
|
|
test_accg_immed 0x7f,accg1
|
|
test_acc_limmed 0xffff,0xffff,acc1
|
|
test_accg_immed 0x7f,accg2
|
|
test_acc_limmed 0xffff,0xffff,acc2
|
|
test_accg_immed 0x7f,accg3
|
|
test_acc_limmed 0xffff,0xffff,acc3
|
|
|
|
set_accg_immed 0x80,accg0 ; saturation
|
|
set_acc_immed 0,acc0
|
|
set_accg_immed 0x80,accg1
|
|
set_acc_immed 0,acc1
|
|
set_accg_immed 0x80,accg2 ; saturation
|
|
set_acc_immed 0,acc2
|
|
set_accg_immed 0x80,accg3
|
|
set_acc_immed 0,acc3
|
|
set_fr_iimmed 0xffff,0,fr8
|
|
set_fr_iimmed 1,0xffff,fr10
|
|
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,0
|
|
test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set
|
|
test_spr_bits 2,1,1,msr0 ; msr0.ovf is set
|
|
test_spr_bits 1,0,1,msr0 ; msr0.aovf is set
|
|
test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set
|
|
test_accg_immed 0x80,accg0
|
|
test_acc_immed 0,acc0
|
|
test_accg_immed 0x80,accg1
|
|
test_acc_immed 0,acc1
|
|
test_accg_immed 0x80,accg2
|
|
test_acc_immed 0,acc2
|
|
test_accg_immed 0x80,accg3
|
|
test_acc_immed 0,acc3
|
|
|
|
; Positive operands
|
|
set_spr_immed 0,msr0
|
|
set_spr_immed 0,msr1
|
|
set_accg_immed 0x00000011,accg0
|
|
set_acc_immed 0x11111111,acc0
|
|
set_accg_immed 0x00000022,accg1
|
|
set_acc_immed 0x22222222,acc1
|
|
set_accg_immed 0x00000033,accg2
|
|
set_acc_immed 0x33333333,acc2
|
|
set_accg_immed 0x00000044,accg3
|
|
set_acc_immed 0x44444444,acc3
|
|
set_fr_iimmed 2,3,fr8 ; multiply small numbers
|
|
set_fr_iimmed 3,2,fr10
|
|
set_fr_iimmed 0,1,fr9 ; multiply by 0
|
|
set_fr_iimmed 2,0,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 2,1,fr8 ; multiply by 1
|
|
set_fr_iimmed 1,2,fr10
|
|
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
|
|
set_fr_iimmed 2,0x3fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
|
|
set_fr_iimmed 2,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
; Mixed operands
|
|
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,2,fr10
|
|
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
|
|
set_fr_iimmed 1,0xfffe,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
|
|
set_fr_iimmed 0,0xfffe,fr10
|
|
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
|
|
set_fr_iimmed 0xfffe,0x2001,fr11
|
|
cmqmachs fr8,fr10,acc0,cc0,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
|
|
set_fr_iimmed 0xfffe,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
|
|
set_fr_iimmed 0x8000,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
; Negative operands
|
|
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,0xfffe,fr10
|
|
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
|
|
set_fr_iimmed 0xfffe,0xffff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
|
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
|
|
set_fr_iimmed 0x8000,0x8000,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_accg_immed 0x7f,accg0 ; saturation
|
|
set_acc_immed 0xffffffff,acc0
|
|
set_accg_immed 0x7f,accg1
|
|
set_acc_immed 0xffffffff,acc1
|
|
set_accg_immed 0x7f,accg2 ; saturation
|
|
set_acc_immed 0xffffffff,acc2
|
|
set_accg_immed 0x7f,accg3
|
|
set_acc_immed 0xffffffff,acc3
|
|
set_fr_iimmed 1,1,fr8
|
|
set_fr_iimmed 1,1,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x7f,accg0 ; saturation
|
|
test_acc_immed 0xffffffff,acc0
|
|
test_accg_immed 0x7f,accg1
|
|
test_acc_immed 0xffffffff,acc1
|
|
test_accg_immed 0x7f,accg2 ; saturation
|
|
test_acc_immed 0xffffffff,acc2
|
|
test_accg_immed 0x7f,accg3
|
|
test_acc_immed 0xffffffff,acc3
|
|
|
|
set_accg_immed 0x80,accg0 ; saturation
|
|
set_acc_immed 0,acc0
|
|
set_accg_immed 0x80,accg1
|
|
set_acc_immed 0,acc1
|
|
set_accg_immed 0x80,accg2 ; saturation
|
|
set_acc_immed 0,acc2
|
|
set_accg_immed 0x80,accg3
|
|
set_acc_immed 0,acc3
|
|
set_fr_iimmed 0xffff,0,fr8
|
|
set_fr_iimmed 1,0xffff,fr10
|
|
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc4,0
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x80,accg0 ; saturation
|
|
test_acc_immed 0,acc0
|
|
test_accg_immed 0x80,accg1
|
|
test_acc_immed 0,acc1
|
|
test_accg_immed 0x80,accg2 ; saturation
|
|
test_acc_immed 0,acc2
|
|
test_accg_immed 0x80,accg3
|
|
test_acc_immed 0,acc3
|
|
|
|
; Positive operands
|
|
set_spr_immed 0,msr0
|
|
set_spr_immed 0,msr1
|
|
set_accg_immed 0x00000011,accg0
|
|
set_acc_immed 0x11111111,acc0
|
|
set_accg_immed 0x00000022,accg1
|
|
set_acc_immed 0x22222222,acc1
|
|
set_accg_immed 0x00000033,accg2
|
|
set_acc_immed 0x33333333,acc2
|
|
set_accg_immed 0x00000044,accg3
|
|
set_acc_immed 0x44444444,acc3
|
|
set_fr_iimmed 2,3,fr8 ; multiply small numbers
|
|
set_fr_iimmed 3,2,fr10
|
|
set_fr_iimmed 0,1,fr9 ; multiply by 0
|
|
set_fr_iimmed 2,0,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 2,1,fr8 ; multiply by 1
|
|
set_fr_iimmed 1,2,fr10
|
|
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
|
|
set_fr_iimmed 2,0x3fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
|
|
set_fr_iimmed 2,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
; Mixed operands
|
|
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,2,fr10
|
|
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
|
|
set_fr_iimmed 1,0xfffe,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
|
|
set_fr_iimmed 0,0xfffe,fr10
|
|
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
|
|
set_fr_iimmed 0xfffe,0x2001,fr11
|
|
cmqmachs fr8,fr10,acc0,cc1,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
|
|
set_fr_iimmed 0xfffe,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
|
|
set_fr_iimmed 0x8000,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
; Negative operands
|
|
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,0xfffe,fr10
|
|
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
|
|
set_fr_iimmed 0xfffe,0xffff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
|
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
|
|
set_fr_iimmed 0x8000,0x8000,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_accg_immed 0x7f,accg0 ; saturation
|
|
set_acc_immed 0xffffffff,acc0
|
|
set_accg_immed 0x7f,accg1
|
|
set_acc_immed 0xffffffff,acc1
|
|
set_accg_immed 0x7f,accg2 ; saturation
|
|
set_acc_immed 0xffffffff,acc2
|
|
set_accg_immed 0x7f,accg3
|
|
set_acc_immed 0xffffffff,acc3
|
|
set_fr_iimmed 1,1,fr8
|
|
set_fr_iimmed 1,1,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x7f,accg0 ; saturation
|
|
test_acc_immed 0xffffffff,acc0
|
|
test_accg_immed 0x7f,accg1
|
|
test_acc_immed 0xffffffff,acc1
|
|
test_accg_immed 0x7f,accg2 ; saturation
|
|
test_acc_immed 0xffffffff,acc2
|
|
test_accg_immed 0x7f,accg3
|
|
test_acc_immed 0xffffffff,acc3
|
|
|
|
set_accg_immed 0x80,accg0 ; saturation
|
|
set_acc_immed 0,acc0
|
|
set_accg_immed 0x80,accg1
|
|
set_acc_immed 0,acc1
|
|
set_accg_immed 0x80,accg2 ; saturation
|
|
set_acc_immed 0,acc2
|
|
set_accg_immed 0x80,accg3
|
|
set_acc_immed 0,acc3
|
|
set_fr_iimmed 0xffff,0,fr8
|
|
set_fr_iimmed 1,0xffff,fr10
|
|
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc5,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x80,accg0 ; saturation
|
|
test_acc_immed 0,acc0
|
|
test_accg_immed 0x80,accg1
|
|
test_acc_immed 0,acc1
|
|
test_accg_immed 0x80,accg2 ; saturation
|
|
test_acc_immed 0,acc2
|
|
test_accg_immed 0x80,accg3
|
|
test_acc_immed 0,acc3
|
|
|
|
; Positive operands
|
|
set_spr_immed 0,msr0
|
|
set_spr_immed 0,msr1
|
|
set_accg_immed 0x00000011,accg0
|
|
set_acc_immed 0x11111111,acc0
|
|
set_accg_immed 0x00000022,accg1
|
|
set_acc_immed 0x22222222,acc1
|
|
set_accg_immed 0x00000033,accg2
|
|
set_acc_immed 0x33333333,acc2
|
|
set_accg_immed 0x00000044,accg3
|
|
set_acc_immed 0x44444444,acc3
|
|
set_fr_iimmed 2,3,fr8 ; multiply small numbers
|
|
set_fr_iimmed 3,2,fr10
|
|
set_fr_iimmed 0,1,fr9 ; multiply by 0
|
|
set_fr_iimmed 2,0,fr11
|
|
cmqmachs fr8,fr10,acc0,cc2,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 2,1,fr8 ; multiply by 1
|
|
set_fr_iimmed 1,2,fr10
|
|
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
|
|
set_fr_iimmed 2,0x3fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc2,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
|
|
set_fr_iimmed 2,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc2,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
; Mixed operands
|
|
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,2,fr10
|
|
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
|
|
set_fr_iimmed 1,0xfffe,fr11
|
|
cmqmachs fr8,fr10,acc0,cc2,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
|
|
set_fr_iimmed 0,0xfffe,fr10
|
|
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
|
|
set_fr_iimmed 0xfffe,0x2001,fr11
|
|
cmqmachs fr8,fr10,acc0,cc2,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
|
|
set_fr_iimmed 0xfffe,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
|
|
set_fr_iimmed 0x8000,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc6,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
; Negative operands
|
|
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,0xfffe,fr10
|
|
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
|
|
set_fr_iimmed 0xfffe,0xffff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc6,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
|
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
|
|
set_fr_iimmed 0x8000,0x8000,fr11
|
|
cmqmachs fr8,fr10,acc0,cc6,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_accg_immed 0x7f,accg0 ; saturation
|
|
set_acc_immed 0xffffffff,acc0
|
|
set_accg_immed 0x7f,accg1
|
|
set_acc_immed 0xffffffff,acc1
|
|
set_accg_immed 0x7f,accg2 ; saturation
|
|
set_acc_immed 0xffffffff,acc2
|
|
set_accg_immed 0x7f,accg3
|
|
set_acc_immed 0xffffffff,acc3
|
|
set_fr_iimmed 1,1,fr8
|
|
set_fr_iimmed 1,1,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc6,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x7f,accg0 ; saturation
|
|
test_acc_immed 0xffffffff,acc0
|
|
test_accg_immed 0x7f,accg1
|
|
test_acc_immed 0xffffffff,acc1
|
|
test_accg_immed 0x7f,accg2 ; saturation
|
|
test_acc_immed 0xffffffff,acc2
|
|
test_accg_immed 0x7f,accg3
|
|
test_acc_immed 0xffffffff,acc3
|
|
|
|
set_accg_immed 0x80,accg0 ; saturation
|
|
set_acc_immed 0,acc0
|
|
set_accg_immed 0x80,accg1
|
|
set_acc_immed 0,acc1
|
|
set_accg_immed 0x80,accg2 ; saturation
|
|
set_acc_immed 0,acc2
|
|
set_accg_immed 0x80,accg3
|
|
set_acc_immed 0,acc3
|
|
set_fr_iimmed 0xffff,0,fr8
|
|
set_fr_iimmed 1,0xffff,fr10
|
|
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc6,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x80,accg0 ; saturation
|
|
test_acc_immed 0,acc0
|
|
test_accg_immed 0x80,accg1
|
|
test_acc_immed 0,acc1
|
|
test_accg_immed 0x80,accg2 ; saturation
|
|
test_acc_immed 0,acc2
|
|
test_accg_immed 0x80,accg3
|
|
test_acc_immed 0,acc3
|
|
;
|
|
; Positive operands
|
|
set_spr_immed 0,msr0
|
|
set_spr_immed 0,msr1
|
|
set_accg_immed 0x00000011,accg0
|
|
set_acc_immed 0x11111111,acc0
|
|
set_accg_immed 0x00000022,accg1
|
|
set_acc_immed 0x22222222,acc1
|
|
set_accg_immed 0x00000033,accg2
|
|
set_acc_immed 0x33333333,acc2
|
|
set_accg_immed 0x00000044,accg3
|
|
set_acc_immed 0x44444444,acc3
|
|
set_fr_iimmed 2,3,fr8 ; multiply small numbers
|
|
set_fr_iimmed 3,2,fr10
|
|
set_fr_iimmed 0,1,fr9 ; multiply by 0
|
|
set_fr_iimmed 2,0,fr11
|
|
cmqmachs fr8,fr10,acc0,cc3,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 2,1,fr8 ; multiply by 1
|
|
set_fr_iimmed 1,2,fr10
|
|
set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result
|
|
set_fr_iimmed 2,0x3fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc3,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x4000,2,fr8 ; 16 bit result
|
|
set_fr_iimmed 2,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc3,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
; Mixed operands
|
|
set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,2,fr10
|
|
set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1
|
|
set_fr_iimmed 1,0xfffe,fr11
|
|
cmqmachs fr8,fr10,acc0,cc3,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0
|
|
set_fr_iimmed 0,0xfffe,fr10
|
|
set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result
|
|
set_fr_iimmed 0xfffe,0x2001,fr11
|
|
cmqmachs fr8,fr10,acc0,cc3,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result
|
|
set_fr_iimmed 0xfffe,0x4000,fr10
|
|
set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result
|
|
set_fr_iimmed 0x8000,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc7,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
; Negative operands
|
|
set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers
|
|
set_fr_iimmed 0xfffd,0xfffe,fr10
|
|
set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1
|
|
set_fr_iimmed 0xfffe,0xffff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc7,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result
|
|
set_fr_iimmed 0x8001,0x8001,fr10
|
|
set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result
|
|
set_fr_iimmed 0x8000,0x8000,fr11
|
|
cmqmachs fr8,fr10,acc0,cc7,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x00000011,accg0
|
|
test_acc_immed 0x11111111,acc0
|
|
test_accg_immed 0x00000022,accg1
|
|
test_acc_immed 0x22222222,acc1
|
|
test_accg_immed 0x00000033,accg2
|
|
test_acc_immed 0x33333333,acc2
|
|
test_accg_immed 0x00000044,accg3
|
|
test_acc_immed 0x44444444,acc3
|
|
|
|
set_accg_immed 0x7f,accg0 ; saturation
|
|
set_acc_immed 0xffffffff,acc0
|
|
set_accg_immed 0x7f,accg1
|
|
set_acc_immed 0xffffffff,acc1
|
|
set_accg_immed 0x7f,accg2 ; saturation
|
|
set_acc_immed 0xffffffff,acc2
|
|
set_accg_immed 0x7f,accg3
|
|
set_acc_immed 0xffffffff,acc3
|
|
set_fr_iimmed 1,1,fr8
|
|
set_fr_iimmed 1,1,fr10
|
|
set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc7,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x7f,accg0 ; saturation
|
|
test_acc_immed 0xffffffff,acc0
|
|
test_accg_immed 0x7f,accg1
|
|
test_acc_immed 0xffffffff,acc1
|
|
test_accg_immed 0x7f,accg2 ; saturation
|
|
test_acc_immed 0xffffffff,acc2
|
|
test_accg_immed 0x7f,accg3
|
|
test_acc_immed 0xffffffff,acc3
|
|
|
|
set_accg_immed 0x80,accg0 ; saturation
|
|
set_acc_immed 0,acc0
|
|
set_accg_immed 0x80,accg1
|
|
set_acc_immed 0,acc1
|
|
set_accg_immed 0x80,accg2 ; saturation
|
|
set_acc_immed 0,acc2
|
|
set_accg_immed 0x80,accg3
|
|
set_acc_immed 0,acc3
|
|
set_fr_iimmed 0xffff,0,fr8
|
|
set_fr_iimmed 1,0xffff,fr10
|
|
set_fr_iimmed 0x0000,0x8000,fr9 ; saturation
|
|
set_fr_iimmed 0x7fff,0x7fff,fr11
|
|
cmqmachs fr8,fr10,acc0,cc7,1
|
|
test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
|
|
test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
|
|
test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
|
|
test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
|
|
test_accg_immed 0x80,accg0 ; saturation
|
|
test_acc_immed 0,acc0
|
|
test_accg_immed 0x80,accg1
|
|
test_acc_immed 0,acc1
|
|
test_accg_immed 0x80,accg2 ; saturation
|
|
test_acc_immed 0,acc2
|
|
test_accg_immed 0x80,accg3
|
|
test_acc_immed 0,acc3
|
|
|
|
pass
|
|
|
|
|