derek.holloway
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290 lines
11 KiB
Plaintext
290 lines
11 KiB
Plaintext
# frv testcase for mp_exception
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# mach: fr500 fr550 frv
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# xerror:
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# This program no longer assembles because the assembler
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# now detects the unaligned registers. For this reason
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# this test is now marked as "xerror" and prints the
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# expected message "fail"
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.include "testutils.inc"
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start
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.global mp_exception
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mpx:
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.if 1
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fail
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.else
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned
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test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mcmpsh.p fr10,fr11,fcc0 ; no exception
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mcmpsh fr10,fr11,fcc2 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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mmulhs.p fr10,fr11,acc3 ; no exception
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mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mmulhu fr10,fr11,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mmulxhs.p fr10,fr11,acc3 ; no exception
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mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mmulxhu fr10,fr11,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mmachs.p fr10,fr11,acc3 ; no exception
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mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mmachu fr10,fr11,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned
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mqaddhss fr10,fr12,fr14 ; no exception
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqaddhss.p fr10,fr12,fr14 ; no exception
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mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned
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mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqaddhss fr10,fr12,fr14 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqmulhs.p fr10,fr11,acc3 ; no exception
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mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqmulhu fr10,fr12,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqmulxhs.p fr10,fr11,acc3 ; no exception
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mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqmulxhu fr10,fr12,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqmachs.p fr10,fr12,acc3 ; no exception
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mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
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mqmachu fr10,fr12,acc0 ; no exception
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqmachu.p fr10,fr12,acc0 ; no exception
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mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
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mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqmachu fr10,fr12,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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mqcpxrs.p fr10,fr12,acc0 ; no exception
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mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned
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test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
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mqcpxru fr10,fr12,acc0 ; no exception
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqcpxru.p fr10,fr12,acc0 ; no exception
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mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned
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mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned
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test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
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or_spr_immed 2,msr0 ; Set msr0.ovf
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or_spr_immed 2,msr1 ; Set msr1.ovf
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and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt
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mqcpxru fr10,fr12,acc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
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test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
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test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set
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pass
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.endif
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