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82 lines
2.3 KiB
Plaintext
82 lines
2.3 KiB
Plaintext
# frv testcase to generate reset interrupts
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# mach: fr500 fr550 fr400
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# sim: --memory-region 0xff000000,64
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.include "testutils.inc"
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start
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.global reset
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reset:
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and_spr_immed 0xfffffffb,psr ; turn off PSR.S
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set_gr_immed 0xfeff0500,gr10 ; address of reset register
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set_spr_immed 0x7fffffff,lcr
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set_bctrlr_0_0 gr0
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; Can't recover from hardware interrupt with enough state intact to verify it
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; set_spr_addr ok1,lr
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; set_mem_immed 0x3,gr10 ; cause hardware reset
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; dcf @(gr10,gr0) ; Wait for store to happen
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; fail
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;
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;ok1: ; reset should branch to reset address which should then branch here
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; test_mem_immed 0x00000200,gr10
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; set_spr_addr ok2,lr
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; set_mem_immed 0x2,gr10 ; cause hardware reset
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; dcf @(gr10,gr0) ; Wait for store to happen
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; fail
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;
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ok2: ; reset should branch to reset address which should then branch here
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; test_mem_immed 0x00000200,gr10
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set_spr_addr ok3,lr
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set_mem_immed 0x1,gr10 ; cause software reset
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dcf @(gr10,gr0) ; Wait for store to happen
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fail
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ok3: ; reset should branch to reset address which should then branch here
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test_mem_immed 0x00000100,gr10
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test_spr_bits 0x4,2,1,psr ; psr.s is set
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test_spr_bits 0x2,1,0,psr ; psr.ps not set
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set_spr_addr bad,lr
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set_mem_immed 0x0,gr10 ; no reset
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test_mem_immed 0x0,gr10
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; now retest with HSR0.SA set
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set_mem_immed 0,gr0
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set_gr_addr 0xff000000,gr11
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set_bctrlr_0_0 gr11
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or_spr_immed 0x00001000,hsr0 ; set HSR0.SA
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; Can't recover from hardware interrupt with enough state intact to verify it
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; set_spr_addr ok4,lr
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; dcf @(gr10,gr0) ; Wait for store to happen
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; set_mem_immed 0x3,gr10 ; cause hardware reset
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; fail
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;
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;ok4: ; reset should branch to reset address which should then branch here
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; test_mem_immed 0x00000200,gr10
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; set_spr_addr ok5,lr
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; set_mem_immed 0x2,gr10 ; cause hardware reset
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; dcf @(gr10,gr0) ; Wait for store to happen
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; fail
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;
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ok5: ; reset should branch to reset address which should then branch here
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; test_mem_immed 0x00000200,gr10
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set_spr_addr ok6,lr
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set_mem_immed 0x1,gr10 ; cause software reset
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dcf @(gr10,gr0) ; Wait for store to happen
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fail
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ok6: ; reset should branch to reset address which should then branch here
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test_mem_immed 0x00000100,gr10
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test_spr_bits 0x4,2,1,psr ; psr.s is set
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test_spr_bits 0x2,1,1,psr ; psr.ps is set
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set_spr_addr bad,lr
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set_mem_immed 0x0,gr10 ; no reset
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test_mem_immed 0x0,gr10
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pass
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bad: ; Should never get here
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fail
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